162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci#ifndef _SPARC64_ESTATE_H 362306a36Sopenharmony_ci#define _SPARC64_ESTATE_H 462306a36Sopenharmony_ci 562306a36Sopenharmony_ci/* UltraSPARC-III E-cache Error Enable */ 662306a36Sopenharmony_ci#define ESTATE_ERROR_FMT 0x0000000000040000 /* Force MTAG ECC */ 762306a36Sopenharmony_ci#define ESTATE_ERROR_FMESS 0x000000000003c000 /* Forced MTAG ECC val */ 862306a36Sopenharmony_ci#define ESTATE_ERROR_FMD 0x0000000000002000 /* Force DATA ECC */ 962306a36Sopenharmony_ci#define ESTATE_ERROR_FDECC 0x0000000000001ff0 /* Forced DATA ECC val */ 1062306a36Sopenharmony_ci#define ESTATE_ERROR_UCEEN 0x0000000000000008 /* See below */ 1162306a36Sopenharmony_ci#define ESTATE_ERROR_NCEEN 0x0000000000000002 /* See below */ 1262306a36Sopenharmony_ci#define ESTATE_ERROR_CEEN 0x0000000000000001 /* See below */ 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci/* UCEEN enables the fast_ECC_error trap for: 1) software correctable E-cache 1562306a36Sopenharmony_ci * errors 2) uncorrectable E-cache errors. Such events only occur on reads 1662306a36Sopenharmony_ci * of the E-cache by the local processor for: 1) data loads 2) instruction 1762306a36Sopenharmony_ci * fetches 3) atomic operations. Such events _cannot_ occur for: 1) merge 1862306a36Sopenharmony_ci * 2) writeback 2) copyout. The AFSR bits associated with these traps are 1962306a36Sopenharmony_ci * UCC and UCU. 2062306a36Sopenharmony_ci */ 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci/* NCEEN enables instruction_access_error, data_access_error, and ECC_error traps 2362306a36Sopenharmony_ci * for uncorrectable ECC errors and system errors. 2462306a36Sopenharmony_ci * 2562306a36Sopenharmony_ci * Uncorrectable system bus data error or MTAG ECC error, system bus TimeOUT, 2662306a36Sopenharmony_ci * or system bus BusERR: 2762306a36Sopenharmony_ci * 1) As the result of an instruction fetch, will generate instruction_access_error 2862306a36Sopenharmony_ci * 2) As the result of a load etc. will generate data_access_error. 2962306a36Sopenharmony_ci * 3) As the result of store merge completion, writeback, or copyout will 3062306a36Sopenharmony_ci * generate a disrupting ECC_error trap. 3162306a36Sopenharmony_ci * 4) As the result of such errors on instruction vector fetch can generate any 3262306a36Sopenharmony_ci * of the 3 trap types. 3362306a36Sopenharmony_ci * 3462306a36Sopenharmony_ci * The AFSR bits associated with these traps are EMU, EDU, WDU, CPU, IVU, UE, 3562306a36Sopenharmony_ci * BERR, and TO. 3662306a36Sopenharmony_ci */ 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ci/* CEEN enables the ECC_error trap for hardware corrected ECC errors. System bus 3962306a36Sopenharmony_ci * reads resulting in a hardware corrected data or MTAG ECC error will generate an 4062306a36Sopenharmony_ci * ECC_error disrupting trap with this bit enabled. 4162306a36Sopenharmony_ci * 4262306a36Sopenharmony_ci * This same trap will also be generated when a hardware corrected ECC error results 4362306a36Sopenharmony_ci * during store merge, writeback, and copyout operations. 4462306a36Sopenharmony_ci */ 4562306a36Sopenharmony_ci 4662306a36Sopenharmony_ci/* In general, if the trap enable bits above are disabled the AFSR bits will still 4762306a36Sopenharmony_ci * log the events even though the trap will not be generated by the processor. 4862306a36Sopenharmony_ci */ 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ci#endif /* _SPARC64_ESTATE_H */ 51