162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * arch/sh/kernel/cpu/sh3/clock-sh7705.c
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * SH7705 support for the clock framework
662306a36Sopenharmony_ci *
762306a36Sopenharmony_ci *  Copyright (C) 2005  Paul Mundt
862306a36Sopenharmony_ci *
962306a36Sopenharmony_ci * FRQCR parsing hacked out of arch/sh/kernel/time.c
1062306a36Sopenharmony_ci *
1162306a36Sopenharmony_ci *  Copyright (C) 1999  Tetsuya Okada & Niibe Yutaka
1262306a36Sopenharmony_ci *  Copyright (C) 2000  Philipp Rumpf <prumpf@tux.org>
1362306a36Sopenharmony_ci *  Copyright (C) 2002, 2003, 2004  Paul Mundt
1462306a36Sopenharmony_ci *  Copyright (C) 2002  M. R. Brown  <mrbrown@linux-sh.org>
1562306a36Sopenharmony_ci */
1662306a36Sopenharmony_ci#include <linux/init.h>
1762306a36Sopenharmony_ci#include <linux/kernel.h>
1862306a36Sopenharmony_ci#include <asm/clock.h>
1962306a36Sopenharmony_ci#include <asm/freq.h>
2062306a36Sopenharmony_ci#include <asm/io.h>
2162306a36Sopenharmony_ci
2262306a36Sopenharmony_ci/*
2362306a36Sopenharmony_ci * SH7705 uses the same divisors as the generic SH-3 case, it's just the
2462306a36Sopenharmony_ci * FRQCR layout that is a bit different..
2562306a36Sopenharmony_ci */
2662306a36Sopenharmony_cistatic int stc_multipliers[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
2762306a36Sopenharmony_cistatic int ifc_divisors[]    = { 1, 2, 3, 4, 1, 1, 1, 1 };
2862306a36Sopenharmony_cistatic int pfc_divisors[]    = { 1, 2, 3, 4, 6, 1, 1, 1 };
2962306a36Sopenharmony_ci
3062306a36Sopenharmony_cistatic void master_clk_init(struct clk *clk)
3162306a36Sopenharmony_ci{
3262306a36Sopenharmony_ci	clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003];
3362306a36Sopenharmony_ci}
3462306a36Sopenharmony_ci
3562306a36Sopenharmony_cistatic struct sh_clk_ops sh7705_master_clk_ops = {
3662306a36Sopenharmony_ci	.init		= master_clk_init,
3762306a36Sopenharmony_ci};
3862306a36Sopenharmony_ci
3962306a36Sopenharmony_cistatic unsigned long module_clk_recalc(struct clk *clk)
4062306a36Sopenharmony_ci{
4162306a36Sopenharmony_ci	int idx = __raw_readw(FRQCR) & 0x0003;
4262306a36Sopenharmony_ci	return clk->parent->rate / pfc_divisors[idx];
4362306a36Sopenharmony_ci}
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_cistatic struct sh_clk_ops sh7705_module_clk_ops = {
4662306a36Sopenharmony_ci	.recalc		= module_clk_recalc,
4762306a36Sopenharmony_ci};
4862306a36Sopenharmony_ci
4962306a36Sopenharmony_cistatic unsigned long bus_clk_recalc(struct clk *clk)
5062306a36Sopenharmony_ci{
5162306a36Sopenharmony_ci	int idx = (__raw_readw(FRQCR) & 0x0300) >> 8;
5262306a36Sopenharmony_ci	return clk->parent->rate / stc_multipliers[idx];
5362306a36Sopenharmony_ci}
5462306a36Sopenharmony_ci
5562306a36Sopenharmony_cistatic struct sh_clk_ops sh7705_bus_clk_ops = {
5662306a36Sopenharmony_ci	.recalc		= bus_clk_recalc,
5762306a36Sopenharmony_ci};
5862306a36Sopenharmony_ci
5962306a36Sopenharmony_cistatic unsigned long cpu_clk_recalc(struct clk *clk)
6062306a36Sopenharmony_ci{
6162306a36Sopenharmony_ci	int idx = (__raw_readw(FRQCR) & 0x0030) >> 4;
6262306a36Sopenharmony_ci	return clk->parent->rate / ifc_divisors[idx];
6362306a36Sopenharmony_ci}
6462306a36Sopenharmony_ci
6562306a36Sopenharmony_cistatic struct sh_clk_ops sh7705_cpu_clk_ops = {
6662306a36Sopenharmony_ci	.recalc		= cpu_clk_recalc,
6762306a36Sopenharmony_ci};
6862306a36Sopenharmony_ci
6962306a36Sopenharmony_cistatic struct sh_clk_ops *sh7705_clk_ops[] = {
7062306a36Sopenharmony_ci	&sh7705_master_clk_ops,
7162306a36Sopenharmony_ci	&sh7705_module_clk_ops,
7262306a36Sopenharmony_ci	&sh7705_bus_clk_ops,
7362306a36Sopenharmony_ci	&sh7705_cpu_clk_ops,
7462306a36Sopenharmony_ci};
7562306a36Sopenharmony_ci
7662306a36Sopenharmony_civoid __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
7762306a36Sopenharmony_ci{
7862306a36Sopenharmony_ci	if (idx < ARRAY_SIZE(sh7705_clk_ops))
7962306a36Sopenharmony_ci		*ops = sh7705_clk_ops[idx];
8062306a36Sopenharmony_ci}
8162306a36Sopenharmony_ci
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