162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 262306a36Sopenharmony_ci * 362306a36Sopenharmony_ci * include/asm-sh/cpu-sh4/sq.h 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 2001, 2002, 2003 Paul Mundt 662306a36Sopenharmony_ci * Copyright (C) 2001, 2002 M. R. Brown 762306a36Sopenharmony_ci */ 862306a36Sopenharmony_ci#ifndef __ASM_CPU_SH4_SQ_H 962306a36Sopenharmony_ci#define __ASM_CPU_SH4_SQ_H 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci#include <asm/addrspace.h> 1262306a36Sopenharmony_ci#include <asm/page.h> 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci/* 1562306a36Sopenharmony_ci * Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be 1662306a36Sopenharmony_ci * mapped to any physical address space. Since data is written (and aligned) 1762306a36Sopenharmony_ci * to 32-byte boundaries, we need to be sure that all allocations are aligned. 1862306a36Sopenharmony_ci */ 1962306a36Sopenharmony_ci#define SQ_SIZE 32 2062306a36Sopenharmony_ci#define SQ_ALIGN_MASK (~(SQ_SIZE - 1)) 2162306a36Sopenharmony_ci#define SQ_ALIGN(addr) (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK) 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci#define SQ_QACR0 (P4SEG_REG_BASE + 0x38) 2462306a36Sopenharmony_ci#define SQ_QACR1 (P4SEG_REG_BASE + 0x3c) 2562306a36Sopenharmony_ci#define SQ_ADDRMAX (P4SEG_STORE_QUE + 0x04000000) 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_ci/* arch/sh/kernel/cpu/sh4/sq.c */ 2862306a36Sopenharmony_ciunsigned long sq_remap(unsigned long phys, unsigned int size, 2962306a36Sopenharmony_ci const char *name, pgprot_t prot); 3062306a36Sopenharmony_civoid sq_unmap(unsigned long vaddr); 3162306a36Sopenharmony_civoid sq_flush_range(unsigned long start, unsigned int len); 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ci#endif /* __ASM_CPU_SH4_SQ_H */ 34