162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 262306a36Sopenharmony_ci * 362306a36Sopenharmony_ci * SH3 CPU-specific DMA definitions, used by both DMA drivers 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci#ifndef CPU_DMA_REGISTER_H 862306a36Sopenharmony_ci#define CPU_DMA_REGISTER_H 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci#define CHCR_TS_LOW_MASK 0x18 1162306a36Sopenharmony_ci#define CHCR_TS_LOW_SHIFT 3 1262306a36Sopenharmony_ci#define CHCR_TS_HIGH_MASK 0 1362306a36Sopenharmony_ci#define CHCR_TS_HIGH_SHIFT 0 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ci#define DMAOR_INIT DMAOR_DME 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ci/* 1862306a36Sopenharmony_ci * The SuperH DMAC supports a number of transmit sizes, we list them here, 1962306a36Sopenharmony_ci * with their respective values as they appear in the CHCR registers. 2062306a36Sopenharmony_ci */ 2162306a36Sopenharmony_cienum { 2262306a36Sopenharmony_ci XMIT_SZ_8BIT, 2362306a36Sopenharmony_ci XMIT_SZ_16BIT, 2462306a36Sopenharmony_ci XMIT_SZ_32BIT, 2562306a36Sopenharmony_ci XMIT_SZ_128BIT, 2662306a36Sopenharmony_ci}; 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ci/* log2(size / 8) - used to calculate number of transfers */ 2962306a36Sopenharmony_ci#define TS_SHIFT { \ 3062306a36Sopenharmony_ci [XMIT_SZ_8BIT] = 0, \ 3162306a36Sopenharmony_ci [XMIT_SZ_16BIT] = 1, \ 3262306a36Sopenharmony_ci [XMIT_SZ_32BIT] = 2, \ 3362306a36Sopenharmony_ci [XMIT_SZ_128BIT] = 4, \ 3462306a36Sopenharmony_ci} 3562306a36Sopenharmony_ci 3662306a36Sopenharmony_ci#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT) 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ci#endif 39