162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Renesas Technology Europe SDK7786 Support. 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 2010 Matt Fleming 662306a36Sopenharmony_ci * Copyright (C) 2010 Paul Mundt 762306a36Sopenharmony_ci */ 862306a36Sopenharmony_ci#include <linux/init.h> 962306a36Sopenharmony_ci#include <linux/platform_device.h> 1062306a36Sopenharmony_ci#include <linux/io.h> 1162306a36Sopenharmony_ci#include <linux/regulator/fixed.h> 1262306a36Sopenharmony_ci#include <linux/regulator/machine.h> 1362306a36Sopenharmony_ci#include <linux/smsc911x.h> 1462306a36Sopenharmony_ci#include <linux/i2c.h> 1562306a36Sopenharmony_ci#include <linux/irq.h> 1662306a36Sopenharmony_ci#include <linux/clk.h> 1762306a36Sopenharmony_ci#include <linux/clkdev.h> 1862306a36Sopenharmony_ci#include <mach/fpga.h> 1962306a36Sopenharmony_ci#include <mach/irq.h> 2062306a36Sopenharmony_ci#include <asm/machvec.h> 2162306a36Sopenharmony_ci#include <asm/heartbeat.h> 2262306a36Sopenharmony_ci#include <linux/sizes.h> 2362306a36Sopenharmony_ci#include <asm/clock.h> 2462306a36Sopenharmony_ci#include <asm/reboot.h> 2562306a36Sopenharmony_ci#include <asm/smp-ops.h> 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_cistatic struct resource heartbeat_resource = { 2862306a36Sopenharmony_ci .start = 0x07fff8b0, 2962306a36Sopenharmony_ci .end = 0x07fff8b0 + sizeof(u16) - 1, 3062306a36Sopenharmony_ci .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, 3162306a36Sopenharmony_ci}; 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_cistatic struct platform_device heartbeat_device = { 3462306a36Sopenharmony_ci .name = "heartbeat", 3562306a36Sopenharmony_ci .id = -1, 3662306a36Sopenharmony_ci .num_resources = 1, 3762306a36Sopenharmony_ci .resource = &heartbeat_resource, 3862306a36Sopenharmony_ci}; 3962306a36Sopenharmony_ci 4062306a36Sopenharmony_ci/* Dummy supplies, where voltage doesn't matter */ 4162306a36Sopenharmony_cistatic struct regulator_consumer_supply dummy_supplies[] = { 4262306a36Sopenharmony_ci REGULATOR_SUPPLY("vddvario", "smsc911x"), 4362306a36Sopenharmony_ci REGULATOR_SUPPLY("vdd33a", "smsc911x"), 4462306a36Sopenharmony_ci}; 4562306a36Sopenharmony_ci 4662306a36Sopenharmony_cistatic struct resource smsc911x_resources[] = { 4762306a36Sopenharmony_ci [0] = { 4862306a36Sopenharmony_ci .name = "smsc911x-memory", 4962306a36Sopenharmony_ci .start = 0x07ffff00, 5062306a36Sopenharmony_ci .end = 0x07ffff00 + SZ_256 - 1, 5162306a36Sopenharmony_ci .flags = IORESOURCE_MEM, 5262306a36Sopenharmony_ci }, 5362306a36Sopenharmony_ci [1] = { 5462306a36Sopenharmony_ci .name = "smsc911x-irq", 5562306a36Sopenharmony_ci .start = evt2irq(0x2c0), 5662306a36Sopenharmony_ci .end = evt2irq(0x2c0), 5762306a36Sopenharmony_ci .flags = IORESOURCE_IRQ, 5862306a36Sopenharmony_ci }, 5962306a36Sopenharmony_ci}; 6062306a36Sopenharmony_ci 6162306a36Sopenharmony_cistatic struct smsc911x_platform_config smsc911x_config = { 6262306a36Sopenharmony_ci .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 6362306a36Sopenharmony_ci .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, 6462306a36Sopenharmony_ci .flags = SMSC911X_USE_32BIT, 6562306a36Sopenharmony_ci .phy_interface = PHY_INTERFACE_MODE_MII, 6662306a36Sopenharmony_ci}; 6762306a36Sopenharmony_ci 6862306a36Sopenharmony_cistatic struct platform_device smsc911x_device = { 6962306a36Sopenharmony_ci .name = "smsc911x", 7062306a36Sopenharmony_ci .id = -1, 7162306a36Sopenharmony_ci .num_resources = ARRAY_SIZE(smsc911x_resources), 7262306a36Sopenharmony_ci .resource = smsc911x_resources, 7362306a36Sopenharmony_ci .dev = { 7462306a36Sopenharmony_ci .platform_data = &smsc911x_config, 7562306a36Sopenharmony_ci }, 7662306a36Sopenharmony_ci}; 7762306a36Sopenharmony_ci 7862306a36Sopenharmony_cistatic struct resource smbus_fpga_resource = { 7962306a36Sopenharmony_ci .start = 0x07fff9e0, 8062306a36Sopenharmony_ci .end = 0x07fff9e0 + SZ_32 - 1, 8162306a36Sopenharmony_ci .flags = IORESOURCE_MEM, 8262306a36Sopenharmony_ci}; 8362306a36Sopenharmony_ci 8462306a36Sopenharmony_cistatic struct platform_device smbus_fpga_device = { 8562306a36Sopenharmony_ci .name = "i2c-sdk7786", 8662306a36Sopenharmony_ci .id = 0, 8762306a36Sopenharmony_ci .num_resources = 1, 8862306a36Sopenharmony_ci .resource = &smbus_fpga_resource, 8962306a36Sopenharmony_ci}; 9062306a36Sopenharmony_ci 9162306a36Sopenharmony_cistatic struct resource smbus_pcie_resource = { 9262306a36Sopenharmony_ci .start = 0x07fffc30, 9362306a36Sopenharmony_ci .end = 0x07fffc30 + SZ_32 - 1, 9462306a36Sopenharmony_ci .flags = IORESOURCE_MEM, 9562306a36Sopenharmony_ci}; 9662306a36Sopenharmony_ci 9762306a36Sopenharmony_cistatic struct platform_device smbus_pcie_device = { 9862306a36Sopenharmony_ci .name = "i2c-sdk7786", 9962306a36Sopenharmony_ci .id = 1, 10062306a36Sopenharmony_ci .num_resources = 1, 10162306a36Sopenharmony_ci .resource = &smbus_pcie_resource, 10262306a36Sopenharmony_ci}; 10362306a36Sopenharmony_ci 10462306a36Sopenharmony_cistatic struct i2c_board_info __initdata sdk7786_i2c_devices[] = { 10562306a36Sopenharmony_ci { 10662306a36Sopenharmony_ci I2C_BOARD_INFO("max6900", 0x68), 10762306a36Sopenharmony_ci }, 10862306a36Sopenharmony_ci}; 10962306a36Sopenharmony_ci 11062306a36Sopenharmony_cistatic struct platform_device *sh7786_devices[] __initdata = { 11162306a36Sopenharmony_ci &heartbeat_device, 11262306a36Sopenharmony_ci &smsc911x_device, 11362306a36Sopenharmony_ci &smbus_fpga_device, 11462306a36Sopenharmony_ci &smbus_pcie_device, 11562306a36Sopenharmony_ci}; 11662306a36Sopenharmony_ci 11762306a36Sopenharmony_cistatic int sdk7786_i2c_setup(void) 11862306a36Sopenharmony_ci{ 11962306a36Sopenharmony_ci unsigned int tmp; 12062306a36Sopenharmony_ci 12162306a36Sopenharmony_ci /* 12262306a36Sopenharmony_ci * Hand over I2C control to the FPGA. 12362306a36Sopenharmony_ci */ 12462306a36Sopenharmony_ci tmp = fpga_read_reg(SBCR); 12562306a36Sopenharmony_ci tmp &= ~SCBR_I2CCEN; 12662306a36Sopenharmony_ci tmp |= SCBR_I2CMEN; 12762306a36Sopenharmony_ci fpga_write_reg(tmp, SBCR); 12862306a36Sopenharmony_ci 12962306a36Sopenharmony_ci return i2c_register_board_info(0, sdk7786_i2c_devices, 13062306a36Sopenharmony_ci ARRAY_SIZE(sdk7786_i2c_devices)); 13162306a36Sopenharmony_ci} 13262306a36Sopenharmony_ci 13362306a36Sopenharmony_cistatic int __init sdk7786_devices_setup(void) 13462306a36Sopenharmony_ci{ 13562306a36Sopenharmony_ci int ret; 13662306a36Sopenharmony_ci 13762306a36Sopenharmony_ci ret = platform_add_devices(sh7786_devices, ARRAY_SIZE(sh7786_devices)); 13862306a36Sopenharmony_ci if (unlikely(ret != 0)) 13962306a36Sopenharmony_ci return ret; 14062306a36Sopenharmony_ci 14162306a36Sopenharmony_ci return sdk7786_i2c_setup(); 14262306a36Sopenharmony_ci} 14362306a36Sopenharmony_cidevice_initcall(sdk7786_devices_setup); 14462306a36Sopenharmony_ci 14562306a36Sopenharmony_cistatic int sdk7786_mode_pins(void) 14662306a36Sopenharmony_ci{ 14762306a36Sopenharmony_ci return fpga_read_reg(MODSWR); 14862306a36Sopenharmony_ci} 14962306a36Sopenharmony_ci 15062306a36Sopenharmony_ci/* 15162306a36Sopenharmony_ci * FPGA-driven PCIe clocks 15262306a36Sopenharmony_ci * 15362306a36Sopenharmony_ci * Historically these include the oscillator, clock B (slots 2/3/4) and 15462306a36Sopenharmony_ci * clock A (slot 1 and the CPU clock). Newer revs of the PCB shove 15562306a36Sopenharmony_ci * everything under a single PCIe clocks enable bit that happens to map 15662306a36Sopenharmony_ci * to the same bit position as the oscillator bit for earlier FPGA 15762306a36Sopenharmony_ci * versions. 15862306a36Sopenharmony_ci * 15962306a36Sopenharmony_ci * Given that the legacy clocks have the side-effect of shutting the CPU 16062306a36Sopenharmony_ci * off through the FPGA along with the PCI slots, we simply leave them in 16162306a36Sopenharmony_ci * their initial state and don't bother registering them with the clock 16262306a36Sopenharmony_ci * framework. 16362306a36Sopenharmony_ci */ 16462306a36Sopenharmony_cistatic int sdk7786_pcie_clk_enable(struct clk *clk) 16562306a36Sopenharmony_ci{ 16662306a36Sopenharmony_ci fpga_write_reg(fpga_read_reg(PCIECR) | PCIECR_CLKEN, PCIECR); 16762306a36Sopenharmony_ci return 0; 16862306a36Sopenharmony_ci} 16962306a36Sopenharmony_ci 17062306a36Sopenharmony_cistatic void sdk7786_pcie_clk_disable(struct clk *clk) 17162306a36Sopenharmony_ci{ 17262306a36Sopenharmony_ci fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR); 17362306a36Sopenharmony_ci} 17462306a36Sopenharmony_ci 17562306a36Sopenharmony_cistatic struct sh_clk_ops sdk7786_pcie_clk_ops = { 17662306a36Sopenharmony_ci .enable = sdk7786_pcie_clk_enable, 17762306a36Sopenharmony_ci .disable = sdk7786_pcie_clk_disable, 17862306a36Sopenharmony_ci}; 17962306a36Sopenharmony_ci 18062306a36Sopenharmony_cistatic struct clk sdk7786_pcie_clk = { 18162306a36Sopenharmony_ci .ops = &sdk7786_pcie_clk_ops, 18262306a36Sopenharmony_ci}; 18362306a36Sopenharmony_ci 18462306a36Sopenharmony_cistatic struct clk_lookup sdk7786_pcie_cl = { 18562306a36Sopenharmony_ci .con_id = "pcie_plat_clk", 18662306a36Sopenharmony_ci .clk = &sdk7786_pcie_clk, 18762306a36Sopenharmony_ci}; 18862306a36Sopenharmony_ci 18962306a36Sopenharmony_cistatic int sdk7786_clk_init(void) 19062306a36Sopenharmony_ci{ 19162306a36Sopenharmony_ci struct clk *clk; 19262306a36Sopenharmony_ci int ret; 19362306a36Sopenharmony_ci 19462306a36Sopenharmony_ci /* 19562306a36Sopenharmony_ci * Only handle the EXTAL case, anyone interfacing a crystal 19662306a36Sopenharmony_ci * resonator will need to provide their own input clock. 19762306a36Sopenharmony_ci */ 19862306a36Sopenharmony_ci if (test_mode_pin(MODE_PIN9)) 19962306a36Sopenharmony_ci return -EINVAL; 20062306a36Sopenharmony_ci 20162306a36Sopenharmony_ci clk = clk_get(NULL, "extal"); 20262306a36Sopenharmony_ci if (IS_ERR(clk)) 20362306a36Sopenharmony_ci return PTR_ERR(clk); 20462306a36Sopenharmony_ci ret = clk_set_rate(clk, 33333333); 20562306a36Sopenharmony_ci clk_put(clk); 20662306a36Sopenharmony_ci 20762306a36Sopenharmony_ci /* 20862306a36Sopenharmony_ci * Setup the FPGA clocks. 20962306a36Sopenharmony_ci */ 21062306a36Sopenharmony_ci ret = clk_register(&sdk7786_pcie_clk); 21162306a36Sopenharmony_ci if (unlikely(ret)) { 21262306a36Sopenharmony_ci pr_err("FPGA clock registration failed\n"); 21362306a36Sopenharmony_ci return ret; 21462306a36Sopenharmony_ci } 21562306a36Sopenharmony_ci 21662306a36Sopenharmony_ci clkdev_add(&sdk7786_pcie_cl); 21762306a36Sopenharmony_ci 21862306a36Sopenharmony_ci return 0; 21962306a36Sopenharmony_ci} 22062306a36Sopenharmony_ci 22162306a36Sopenharmony_cistatic void sdk7786_restart(char *cmd) 22262306a36Sopenharmony_ci{ 22362306a36Sopenharmony_ci fpga_write_reg(0xa5a5, SRSTR); 22462306a36Sopenharmony_ci} 22562306a36Sopenharmony_ci 22662306a36Sopenharmony_cistatic void sdk7786_power_off(void) 22762306a36Sopenharmony_ci{ 22862306a36Sopenharmony_ci fpga_write_reg(fpga_read_reg(PWRCR) | PWRCR_PDWNREQ, PWRCR); 22962306a36Sopenharmony_ci 23062306a36Sopenharmony_ci /* 23162306a36Sopenharmony_ci * It can take up to 20us for the R8C to do its job, back off and 23262306a36Sopenharmony_ci * wait a bit until we've been shut off. Even though newer FPGA 23362306a36Sopenharmony_ci * versions don't set the ACK bit, the latency issue remains. 23462306a36Sopenharmony_ci */ 23562306a36Sopenharmony_ci while ((fpga_read_reg(PWRCR) & PWRCR_PDWNACK) == 0) 23662306a36Sopenharmony_ci cpu_sleep(); 23762306a36Sopenharmony_ci} 23862306a36Sopenharmony_ci 23962306a36Sopenharmony_ci/* Initialize the board */ 24062306a36Sopenharmony_cistatic void __init sdk7786_setup(char **cmdline_p) 24162306a36Sopenharmony_ci{ 24262306a36Sopenharmony_ci pr_info("Renesas Technology Europe SDK7786 support:\n"); 24362306a36Sopenharmony_ci 24462306a36Sopenharmony_ci regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); 24562306a36Sopenharmony_ci 24662306a36Sopenharmony_ci sdk7786_fpga_init(); 24762306a36Sopenharmony_ci sdk7786_nmi_init(); 24862306a36Sopenharmony_ci 24962306a36Sopenharmony_ci pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf); 25062306a36Sopenharmony_ci 25162306a36Sopenharmony_ci machine_ops.restart = sdk7786_restart; 25262306a36Sopenharmony_ci pm_power_off = sdk7786_power_off; 25362306a36Sopenharmony_ci 25462306a36Sopenharmony_ci register_smp_ops(&shx3_smp_ops); 25562306a36Sopenharmony_ci} 25662306a36Sopenharmony_ci 25762306a36Sopenharmony_ci/* 25862306a36Sopenharmony_ci * The Machine Vector 25962306a36Sopenharmony_ci */ 26062306a36Sopenharmony_cistatic struct sh_machine_vector mv_sdk7786 __initmv = { 26162306a36Sopenharmony_ci .mv_name = "SDK7786", 26262306a36Sopenharmony_ci .mv_setup = sdk7786_setup, 26362306a36Sopenharmony_ci .mv_mode_pins = sdk7786_mode_pins, 26462306a36Sopenharmony_ci .mv_clk_init = sdk7786_clk_init, 26562306a36Sopenharmony_ci .mv_init_irq = sdk7786_init_irq, 26662306a36Sopenharmony_ci}; 267