1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * S390 version 4 * Copyright IBM Corp. 1999, 2000 5 * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) 6 */ 7#ifndef _S390_PTRACE_H 8#define _S390_PTRACE_H 9 10#include <linux/bits.h> 11#include <uapi/asm/ptrace.h> 12#include <asm/tpi.h> 13 14#define PIF_SYSCALL 0 /* inside a system call */ 15#define PIF_EXECVE_PGSTE_RESTART 1 /* restart execve for PGSTE binaries */ 16#define PIF_SYSCALL_RET_SET 2 /* return value was set via ptrace */ 17#define PIF_GUEST_FAULT 3 /* indicates program check in sie64a */ 18#define PIF_FTRACE_FULL_REGS 4 /* all register contents valid (ftrace) */ 19 20#define _PIF_SYSCALL BIT(PIF_SYSCALL) 21#define _PIF_EXECVE_PGSTE_RESTART BIT(PIF_EXECVE_PGSTE_RESTART) 22#define _PIF_SYSCALL_RET_SET BIT(PIF_SYSCALL_RET_SET) 23#define _PIF_GUEST_FAULT BIT(PIF_GUEST_FAULT) 24#define _PIF_FTRACE_FULL_REGS BIT(PIF_FTRACE_FULL_REGS) 25 26#define PSW32_MASK_PER _AC(0x40000000, UL) 27#define PSW32_MASK_DAT _AC(0x04000000, UL) 28#define PSW32_MASK_IO _AC(0x02000000, UL) 29#define PSW32_MASK_EXT _AC(0x01000000, UL) 30#define PSW32_MASK_KEY _AC(0x00F00000, UL) 31#define PSW32_MASK_BASE _AC(0x00080000, UL) /* Always one */ 32#define PSW32_MASK_MCHECK _AC(0x00040000, UL) 33#define PSW32_MASK_WAIT _AC(0x00020000, UL) 34#define PSW32_MASK_PSTATE _AC(0x00010000, UL) 35#define PSW32_MASK_ASC _AC(0x0000C000, UL) 36#define PSW32_MASK_CC _AC(0x00003000, UL) 37#define PSW32_MASK_PM _AC(0x00000f00, UL) 38#define PSW32_MASK_RI _AC(0x00000080, UL) 39 40#define PSW32_ADDR_AMODE _AC(0x80000000, UL) 41#define PSW32_ADDR_INSN _AC(0x7FFFFFFF, UL) 42 43#define PSW32_DEFAULT_KEY ((PAGE_DEFAULT_ACC) << 20) 44 45#define PSW32_ASC_PRIMARY _AC(0x00000000, UL) 46#define PSW32_ASC_ACCREG _AC(0x00004000, UL) 47#define PSW32_ASC_SECONDARY _AC(0x00008000, UL) 48#define PSW32_ASC_HOME _AC(0x0000C000, UL) 49 50#define PSW_DEFAULT_KEY ((PAGE_DEFAULT_ACC) << 52) 51 52#define PSW_KERNEL_BITS (PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_ASC_HOME | \ 53 PSW_MASK_EA | PSW_MASK_BA | PSW_MASK_DAT) 54#define PSW_USER_BITS (PSW_MASK_DAT | PSW_MASK_IO | PSW_MASK_EXT | \ 55 PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_MASK_MCHECK | \ 56 PSW_MASK_PSTATE | PSW_ASC_PRIMARY) 57 58#ifndef __ASSEMBLY__ 59 60struct psw_bits { 61 unsigned long : 1; 62 unsigned long per : 1; /* PER-Mask */ 63 unsigned long : 3; 64 unsigned long dat : 1; /* DAT Mode */ 65 unsigned long io : 1; /* Input/Output Mask */ 66 unsigned long ext : 1; /* External Mask */ 67 unsigned long key : 4; /* PSW Key */ 68 unsigned long : 1; 69 unsigned long mcheck : 1; /* Machine-Check Mask */ 70 unsigned long wait : 1; /* Wait State */ 71 unsigned long pstate : 1; /* Problem State */ 72 unsigned long as : 2; /* Address Space Control */ 73 unsigned long cc : 2; /* Condition Code */ 74 unsigned long pm : 4; /* Program Mask */ 75 unsigned long ri : 1; /* Runtime Instrumentation */ 76 unsigned long : 6; 77 unsigned long eaba : 2; /* Addressing Mode */ 78 unsigned long : 31; 79 unsigned long ia : 64; /* Instruction Address */ 80}; 81 82enum { 83 PSW_BITS_AMODE_24BIT = 0, 84 PSW_BITS_AMODE_31BIT = 1, 85 PSW_BITS_AMODE_64BIT = 3 86}; 87 88enum { 89 PSW_BITS_AS_PRIMARY = 0, 90 PSW_BITS_AS_ACCREG = 1, 91 PSW_BITS_AS_SECONDARY = 2, 92 PSW_BITS_AS_HOME = 3 93}; 94 95#define psw_bits(__psw) (*({ \ 96 typecheck(psw_t, __psw); \ 97 &(*(struct psw_bits *)(&(__psw))); \ 98})) 99 100typedef struct { 101 unsigned int mask; 102 unsigned int addr; 103} psw_t32 __aligned(8); 104 105#define PGM_INT_CODE_MASK 0x7f 106#define PGM_INT_CODE_PER 0x80 107 108/* 109 * The pt_regs struct defines the way the registers are stored on 110 * the stack during a system call. 111 */ 112struct pt_regs { 113 union { 114 user_pt_regs user_regs; 115 struct { 116 unsigned long args[1]; 117 psw_t psw; 118 unsigned long gprs[NUM_GPRS]; 119 }; 120 }; 121 unsigned long orig_gpr2; 122 union { 123 struct { 124 unsigned int int_code; 125 unsigned int int_parm; 126 unsigned long int_parm_long; 127 }; 128 struct tpi_info tpi_info; 129 }; 130 unsigned long flags; 131 unsigned long cr1; 132 unsigned long last_break; 133}; 134 135/* 136 * Program event recording (PER) register set. 137 */ 138struct per_regs { 139 unsigned long control; /* PER control bits */ 140 unsigned long start; /* PER starting address */ 141 unsigned long end; /* PER ending address */ 142}; 143 144/* 145 * PER event contains information about the cause of the last PER exception. 146 */ 147struct per_event { 148 unsigned short cause; /* PER code, ATMID and AI */ 149 unsigned long address; /* PER address */ 150 unsigned char paid; /* PER access identification */ 151}; 152 153/* 154 * Simplified per_info structure used to decode the ptrace user space ABI. 155 */ 156struct per_struct_kernel { 157 unsigned long cr9; /* PER control bits */ 158 unsigned long cr10; /* PER starting address */ 159 unsigned long cr11; /* PER ending address */ 160 unsigned long bits; /* Obsolete software bits */ 161 unsigned long starting_addr; /* User specified start address */ 162 unsigned long ending_addr; /* User specified end address */ 163 unsigned short perc_atmid; /* PER trap ATMID */ 164 unsigned long address; /* PER trap instruction address */ 165 unsigned char access_id; /* PER trap access identification */ 166}; 167 168#define PER_EVENT_MASK 0xEB000000UL 169 170#define PER_EVENT_BRANCH 0x80000000UL 171#define PER_EVENT_IFETCH 0x40000000UL 172#define PER_EVENT_STORE 0x20000000UL 173#define PER_EVENT_STORE_REAL 0x08000000UL 174#define PER_EVENT_TRANSACTION_END 0x02000000UL 175#define PER_EVENT_NULLIFICATION 0x01000000UL 176 177#define PER_CONTROL_MASK 0x00e00000UL 178 179#define PER_CONTROL_BRANCH_ADDRESS 0x00800000UL 180#define PER_CONTROL_SUSPENSION 0x00400000UL 181#define PER_CONTROL_ALTERATION 0x00200000UL 182 183static inline void set_pt_regs_flag(struct pt_regs *regs, int flag) 184{ 185 regs->flags |= (1UL << flag); 186} 187 188static inline void clear_pt_regs_flag(struct pt_regs *regs, int flag) 189{ 190 regs->flags &= ~(1UL << flag); 191} 192 193static inline int test_pt_regs_flag(struct pt_regs *regs, int flag) 194{ 195 return !!(regs->flags & (1UL << flag)); 196} 197 198static inline int test_and_clear_pt_regs_flag(struct pt_regs *regs, int flag) 199{ 200 int ret = test_pt_regs_flag(regs, flag); 201 202 clear_pt_regs_flag(regs, flag); 203 return ret; 204} 205 206/* 207 * These are defined as per linux/ptrace.h, which see. 208 */ 209#define arch_has_single_step() (1) 210#define arch_has_block_step() (1) 211 212#define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0) 213#define instruction_pointer(regs) ((regs)->psw.addr) 214#define user_stack_pointer(regs)((regs)->gprs[15]) 215#define profile_pc(regs) instruction_pointer(regs) 216 217static inline long regs_return_value(struct pt_regs *regs) 218{ 219 return regs->gprs[2]; 220} 221 222static inline void instruction_pointer_set(struct pt_regs *regs, 223 unsigned long val) 224{ 225 regs->psw.addr = val; 226} 227 228int regs_query_register_offset(const char *name); 229const char *regs_query_register_name(unsigned int offset); 230unsigned long regs_get_register(struct pt_regs *regs, unsigned int offset); 231unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n); 232 233/** 234 * regs_get_kernel_argument() - get Nth function argument in kernel 235 * @regs: pt_regs of that context 236 * @n: function argument number (start from 0) 237 * 238 * regs_get_kernel_argument() returns @n th argument of the function call. 239 */ 240static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs, 241 unsigned int n) 242{ 243 unsigned int argoffset = STACK_FRAME_OVERHEAD / sizeof(long); 244 245#define NR_REG_ARGUMENTS 5 246 if (n < NR_REG_ARGUMENTS) 247 return regs_get_register(regs, 2 + n); 248 n -= NR_REG_ARGUMENTS; 249 return regs_get_kernel_stack_nth(regs, argoffset + n); 250} 251 252static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) 253{ 254 return regs->gprs[15]; 255} 256 257static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc) 258{ 259 regs->gprs[2] = rc; 260} 261 262#endif /* __ASSEMBLY__ */ 263#endif /* _S390_PTRACE_H */ 264