1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2017 SiFive
4 */
5
6#include <linux/of.h>
7#include <asm/cacheflush.h>
8
9#ifdef CONFIG_SMP
10
11#include <asm/sbi.h>
12
13static void ipi_remote_fence_i(void *info)
14{
15	return local_flush_icache_all();
16}
17
18void flush_icache_all(void)
19{
20	local_flush_icache_all();
21
22	if (IS_ENABLED(CONFIG_RISCV_SBI) && !riscv_use_ipi_for_rfence())
23		sbi_remote_fence_i(NULL);
24	else
25		on_each_cpu(ipi_remote_fence_i, NULL, 1);
26}
27EXPORT_SYMBOL(flush_icache_all);
28
29/*
30 * Performs an icache flush for the given MM context.  RISC-V has no direct
31 * mechanism for instruction cache shoot downs, so instead we send an IPI that
32 * informs the remote harts they need to flush their local instruction caches.
33 * To avoid pathologically slow behavior in a common case (a bunch of
34 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
35 * IPIs for harts that are not currently executing a MM context and instead
36 * schedule a deferred local instruction cache flush to be performed before
37 * execution resumes on each hart.
38 */
39void flush_icache_mm(struct mm_struct *mm, bool local)
40{
41	unsigned int cpu;
42	cpumask_t others, *mask;
43
44	preempt_disable();
45
46	/* Mark every hart's icache as needing a flush for this MM. */
47	mask = &mm->context.icache_stale_mask;
48	cpumask_setall(mask);
49	/* Flush this hart's I$ now, and mark it as flushed. */
50	cpu = smp_processor_id();
51	cpumask_clear_cpu(cpu, mask);
52	local_flush_icache_all();
53
54	/*
55	 * Flush the I$ of other harts concurrently executing, and mark them as
56	 * flushed.
57	 */
58	cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
59	local |= cpumask_empty(&others);
60	if (mm == current->active_mm && local) {
61		/*
62		 * It's assumed that at least one strongly ordered operation is
63		 * performed on this hart between setting a hart's cpumask bit
64		 * and scheduling this MM context on that hart.  Sending an SBI
65		 * remote message will do this, but in the case where no
66		 * messages are sent we still need to order this hart's writes
67		 * with flush_icache_deferred().
68		 */
69		smp_mb();
70	} else if (IS_ENABLED(CONFIG_RISCV_SBI) &&
71		   !riscv_use_ipi_for_rfence()) {
72		sbi_remote_fence_i(&others);
73	} else {
74		on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1);
75	}
76
77	preempt_enable();
78}
79
80#endif /* CONFIG_SMP */
81
82#ifdef CONFIG_MMU
83void flush_icache_pte(pte_t pte)
84{
85	struct folio *folio = page_folio(pte_page(pte));
86
87	if (!test_bit(PG_dcache_clean, &folio->flags)) {
88		flush_icache_all();
89		set_bit(PG_dcache_clean, &folio->flags);
90	}
91}
92#endif /* CONFIG_MMU */
93
94unsigned int riscv_cbom_block_size;
95EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
96
97unsigned int riscv_cboz_block_size;
98EXPORT_SYMBOL_GPL(riscv_cboz_block_size);
99
100static void __init cbo_get_block_size(struct device_node *node,
101				      const char *name, u32 *block_size,
102				      unsigned long *first_hartid)
103{
104	unsigned long hartid;
105	u32 val;
106
107	if (riscv_of_processor_hartid(node, &hartid))
108		return;
109
110	if (of_property_read_u32(node, name, &val))
111		return;
112
113	if (!*block_size) {
114		*block_size = val;
115		*first_hartid = hartid;
116	} else if (*block_size != val) {
117		pr_warn("%s mismatched between harts %lu and %lu\n",
118			name, *first_hartid, hartid);
119	}
120}
121
122void __init riscv_init_cbo_blocksizes(void)
123{
124	unsigned long cbom_hartid, cboz_hartid;
125	u32 cbom_block_size = 0, cboz_block_size = 0;
126	struct device_node *node;
127
128	for_each_of_cpu_node(node) {
129		/* set block-size for cbom and/or cboz extension if available */
130		cbo_get_block_size(node, "riscv,cbom-block-size",
131				   &cbom_block_size, &cbom_hartid);
132		cbo_get_block_size(node, "riscv,cboz-block-size",
133				   &cboz_block_size, &cboz_hartid);
134	}
135
136	if (cbom_block_size)
137		riscv_cbom_block_size = cbom_block_size;
138
139	if (cboz_block_size)
140		riscv_cboz_block_size = cboz_block_size;
141}
142