162306a36Sopenharmony_ci// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Device Tree Source for the RZ/Five SoC
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright (C) 2022 Renesas Electronics Corp.
662306a36Sopenharmony_ci */
762306a36Sopenharmony_ci
862306a36Sopenharmony_ci#include <dt-bindings/interrupt-controller/irq.h>
962306a36Sopenharmony_ci
1062306a36Sopenharmony_ci#define SOC_PERIPHERAL_IRQ(nr)	(nr + 32)
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_ci#include <arm64/renesas/r9a07g043.dtsi>
1362306a36Sopenharmony_ci
1462306a36Sopenharmony_ci/ {
1562306a36Sopenharmony_ci	cpus {
1662306a36Sopenharmony_ci		#address-cells = <1>;
1762306a36Sopenharmony_ci		#size-cells = <0>;
1862306a36Sopenharmony_ci		timebase-frequency = <12000000>;
1962306a36Sopenharmony_ci
2062306a36Sopenharmony_ci		cpu0: cpu@0 {
2162306a36Sopenharmony_ci			compatible = "andestech,ax45mp", "riscv";
2262306a36Sopenharmony_ci			device_type = "cpu";
2362306a36Sopenharmony_ci			#cooling-cells = <2>;
2462306a36Sopenharmony_ci			reg = <0x0>;
2562306a36Sopenharmony_ci			status = "okay";
2662306a36Sopenharmony_ci			riscv,isa = "rv64imafdc";
2762306a36Sopenharmony_ci			mmu-type = "riscv,sv39";
2862306a36Sopenharmony_ci			i-cache-size = <0x8000>;
2962306a36Sopenharmony_ci			i-cache-line-size = <0x40>;
3062306a36Sopenharmony_ci			d-cache-size = <0x8000>;
3162306a36Sopenharmony_ci			d-cache-line-size = <0x40>;
3262306a36Sopenharmony_ci			clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
3362306a36Sopenharmony_ci			operating-points-v2 = <&cluster0_opp>;
3462306a36Sopenharmony_ci
3562306a36Sopenharmony_ci			cpu0_intc: interrupt-controller {
3662306a36Sopenharmony_ci				#interrupt-cells = <1>;
3762306a36Sopenharmony_ci				compatible = "riscv,cpu-intc";
3862306a36Sopenharmony_ci				interrupt-controller;
3962306a36Sopenharmony_ci			};
4062306a36Sopenharmony_ci		};
4162306a36Sopenharmony_ci	};
4262306a36Sopenharmony_ci};
4362306a36Sopenharmony_ci
4462306a36Sopenharmony_ci&soc {
4562306a36Sopenharmony_ci	interrupt-parent = <&plic>;
4662306a36Sopenharmony_ci
4762306a36Sopenharmony_ci	plic: interrupt-controller@12c00000 {
4862306a36Sopenharmony_ci		compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
4962306a36Sopenharmony_ci		#interrupt-cells = <2>;
5062306a36Sopenharmony_ci		#address-cells = <0>;
5162306a36Sopenharmony_ci		riscv,ndev = <511>;
5262306a36Sopenharmony_ci		interrupt-controller;
5362306a36Sopenharmony_ci		reg = <0x0 0x12c00000 0 0x400000>;
5462306a36Sopenharmony_ci		clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
5562306a36Sopenharmony_ci		power-domains = <&cpg>;
5662306a36Sopenharmony_ci		resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
5762306a36Sopenharmony_ci		interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
5862306a36Sopenharmony_ci	};
5962306a36Sopenharmony_ci};
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