162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * IPIC private definitions and structure. 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Maintainer: Kumar Gala <galak@kernel.crashing.org> 662306a36Sopenharmony_ci * 762306a36Sopenharmony_ci * Copyright 2005 Freescale Semiconductor, Inc 862306a36Sopenharmony_ci */ 962306a36Sopenharmony_ci#ifndef __IPIC_H__ 1062306a36Sopenharmony_ci#define __IPIC_H__ 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci#include <asm/ipic.h> 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci#define NR_IPIC_INTS 128 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci/* External IRQS */ 1762306a36Sopenharmony_ci#define IPIC_IRQ_EXT0 48 1862306a36Sopenharmony_ci#define IPIC_IRQ_EXT1 17 1962306a36Sopenharmony_ci#define IPIC_IRQ_EXT7 23 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci/* Default Priority Registers */ 2262306a36Sopenharmony_ci#define IPIC_PRIORITY_DEFAULT 0x05309770 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ci/* System Global Interrupt Configuration Register */ 2562306a36Sopenharmony_ci#define SICFR_IPSA 0x00010000 2662306a36Sopenharmony_ci#define SICFR_IPSB 0x00020000 2762306a36Sopenharmony_ci#define SICFR_IPSC 0x00040000 2862306a36Sopenharmony_ci#define SICFR_IPSD 0x00080000 2962306a36Sopenharmony_ci#define SICFR_MPSA 0x00200000 3062306a36Sopenharmony_ci#define SICFR_MPSB 0x00400000 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci/* System External Interrupt Mask Register */ 3362306a36Sopenharmony_ci#define SEMSR_SIRQ0 0x00008000 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci/* System Error Control Register */ 3662306a36Sopenharmony_ci#define SERCR_MCPR 0x00000001 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_cistruct ipic { 3962306a36Sopenharmony_ci volatile u32 __iomem *regs; 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ci /* The remapper for this IPIC */ 4262306a36Sopenharmony_ci struct irq_domain *irqhost; 4362306a36Sopenharmony_ci}; 4462306a36Sopenharmony_ci 4562306a36Sopenharmony_cistruct ipic_info { 4662306a36Sopenharmony_ci u8 ack; /* pending register offset from base if the irq 4762306a36Sopenharmony_ci supports ack operation */ 4862306a36Sopenharmony_ci u8 mask; /* mask register offset from base */ 4962306a36Sopenharmony_ci u8 prio; /* priority register offset from base */ 5062306a36Sopenharmony_ci u8 force; /* force register offset from base */ 5162306a36Sopenharmony_ci u8 bit; /* register bit position (as per doc) 5262306a36Sopenharmony_ci bit mask = 1 << (31 - bit) */ 5362306a36Sopenharmony_ci u8 prio_mask; /* priority mask value */ 5462306a36Sopenharmony_ci}; 5562306a36Sopenharmony_ci 5662306a36Sopenharmony_ci#endif /* __IPIC_H__ */ 57