162306a36Sopenharmony_ci/* 262306a36Sopenharmony_ci * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions 362306a36Sopenharmony_ci * 462306a36Sopenharmony_ci * Copyright (C) 1997 Geert Uytterhoeven 562306a36Sopenharmony_ci * 662306a36Sopenharmony_ci * This file is based on the following documentation: 762306a36Sopenharmony_ci * 862306a36Sopenharmony_ci * The VAS96011/12 Chipset, Data Book, Edition 1.0 962306a36Sopenharmony_ci * VLSI Technology, Inc. 1062306a36Sopenharmony_ci * 1162306a36Sopenharmony_ci * This file is subject to the terms and conditions of the GNU General Public 1262306a36Sopenharmony_ci * License. See the file COPYING in the main directory of this archive 1362306a36Sopenharmony_ci * for more details. 1462306a36Sopenharmony_ci */ 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci#ifndef _ASMPPC_GG2_H 1762306a36Sopenharmony_ci#define _ASMPPC_GG2_H 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci /* 2062306a36Sopenharmony_ci * Memory Map (CHRP mode) 2162306a36Sopenharmony_ci */ 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci#define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */ 2462306a36Sopenharmony_ci#define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */ 2562306a36Sopenharmony_ci#define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */ 2662306a36Sopenharmony_ci#define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */ 2762306a36Sopenharmony_ci#define GG2_INT_ACK_SPECIAL 0xfec80000 /* Interrupt acknowledge and */ 2862306a36Sopenharmony_ci /* special PCI cycles */ 2962306a36Sopenharmony_ci#define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */ 3062306a36Sopenharmony_ci#define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */ 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ci /* 3462306a36Sopenharmony_ci * GG2 specific PCI Registers 3562306a36Sopenharmony_ci */ 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ciextern void __iomem *gg2_pci_config_base; /* kernel virtual address */ 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_ci#define GG2_PCI_BUSNO 0x40 /* Bus number */ 4062306a36Sopenharmony_ci#define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */ 4162306a36Sopenharmony_ci#define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */ 4262306a36Sopenharmony_ci#define GG2_PCI_PPC_CTRL 0x50 /* PowerPC interface control register */ 4362306a36Sopenharmony_ci#define GG2_PCI_ADDR_MAP 0x5c /* Address map */ 4462306a36Sopenharmony_ci#define GG2_PCI_PCI_CTRL 0x60 /* PCI interface control register */ 4562306a36Sopenharmony_ci#define GG2_PCI_ROM_CTRL 0x70 /* ROM interface control register */ 4662306a36Sopenharmony_ci#define GG2_PCI_ROM_TIME 0x74 /* ROM timing */ 4762306a36Sopenharmony_ci#define GG2_PCI_CC_CTRL 0x80 /* Cache controller control register */ 4862306a36Sopenharmony_ci#define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */ 4962306a36Sopenharmony_ci#define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */ 5062306a36Sopenharmony_ci#define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */ 5162306a36Sopenharmony_ci#define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */ 5262306a36Sopenharmony_ci#define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */ 5362306a36Sopenharmony_ci#define GG2_PCI_DRAM_BANK5 0xa4 /* Control register for DRAM bank #5 */ 5462306a36Sopenharmony_ci#define GG2_PCI_DRAM_TIME0 0xb0 /* Timing parameters set #0 */ 5562306a36Sopenharmony_ci#define GG2_PCI_DRAM_TIME1 0xb4 /* Timing parameters set #1 */ 5662306a36Sopenharmony_ci#define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */ 5762306a36Sopenharmony_ci#define GG2_PCI_ERR_CTRL 0xd0 /* Error control register */ 5862306a36Sopenharmony_ci#define GG2_PCI_ERR_STATUS 0xd4 /* Error status register */ 5962306a36Sopenharmony_ci /* Cleared when read */ 6062306a36Sopenharmony_ci 6162306a36Sopenharmony_ci#endif /* _ASMPPC_GG2_H */ 62