1// SPDX-License-Identifier: GPL-2.0 2/* 3 * General Purpose functions for the global management of the 4 * Communication Processor Module. 5 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net) 6 * 7 * In addition to the individual control of the communication 8 * channels, there are a few functions that globally affect the 9 * communication processor. 10 * 11 * Buffer descriptors must be allocated from the dual ported memory 12 * space. The allocator for that is here. When the communication 13 * process is reset, we reclaim the memory available. There is 14 * currently no deallocator for this memory. 15 * The amount of space available is platform dependent. On the 16 * MBX, the EPPC software loads additional microcode into the 17 * communication processor, and uses some of the DP ram for this 18 * purpose. Current, the first 512 bytes and the last 256 bytes of 19 * memory are used. Right now I am conservative and only use the 20 * memory that can never be used for microcode. If there are 21 * applications that require more DP ram, we can expand the boundaries 22 * but then we have to be careful of any downloaded microcode. 23 */ 24#include <linux/errno.h> 25#include <linux/sched.h> 26#include <linux/kernel.h> 27#include <linux/dma-mapping.h> 28#include <linux/param.h> 29#include <linux/string.h> 30#include <linux/mm.h> 31#include <linux/interrupt.h> 32#include <linux/irq.h> 33#include <linux/module.h> 34#include <linux/spinlock.h> 35#include <linux/slab.h> 36#include <linux/of_irq.h> 37#include <asm/page.h> 38#include <asm/8xx_immap.h> 39#include <asm/cpm1.h> 40#include <asm/io.h> 41#include <asm/rheap.h> 42#include <asm/cpm.h> 43 44#include <sysdev/fsl_soc.h> 45 46#ifdef CONFIG_8xx_GPIO 47#include <linux/gpio/legacy-of-mm-gpiochip.h> 48#endif 49 50#define CPM_MAP_SIZE (0x4000) 51 52cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */ 53immap_t __iomem *mpc8xx_immr = (void __iomem *)VIRT_IMMR_BASE; 54 55void __init cpm_reset(void) 56{ 57 cpmp = &mpc8xx_immr->im_cpm; 58 59#ifndef CONFIG_PPC_EARLY_DEBUG_CPM 60 /* Perform a reset. */ 61 out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG); 62 63 /* Wait for it. */ 64 while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG); 65#endif 66 67#ifdef CONFIG_UCODE_PATCH 68 cpm_load_patch(cpmp); 69#endif 70 71 /* 72 * Set SDMA Bus Request priority 5. 73 * On 860T, this also enables FEC priority 6. I am not sure 74 * this is what we really want for some applications, but the 75 * manual recommends it. 76 * Bit 25, FAM can also be set to use FEC aggressive mode (860T). 77 */ 78 if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */ 79 out_be32(&mpc8xx_immr->im_siu_conf.sc_sdcr, 0x40); 80 else 81 out_be32(&mpc8xx_immr->im_siu_conf.sc_sdcr, 1); 82} 83 84static DEFINE_SPINLOCK(cmd_lock); 85 86#define MAX_CR_CMD_LOOPS 10000 87 88int cpm_command(u32 command, u8 opcode) 89{ 90 int i, ret; 91 unsigned long flags; 92 93 if (command & 0xffffff03) 94 return -EINVAL; 95 96 spin_lock_irqsave(&cmd_lock, flags); 97 98 ret = 0; 99 out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8)); 100 for (i = 0; i < MAX_CR_CMD_LOOPS; i++) 101 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0) 102 goto out; 103 104 printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__); 105 ret = -EIO; 106out: 107 spin_unlock_irqrestore(&cmd_lock, flags); 108 return ret; 109} 110EXPORT_SYMBOL(cpm_command); 111 112/* 113 * Set a baud rate generator. This needs lots of work. There are 114 * four BRGs, any of which can be wired to any channel. 115 * The internal baud rate clock is the system clock divided by 16. 116 * This assumes the baudrate is 16x oversampled by the uart. 117 */ 118#define BRG_INT_CLK (get_brgfreq()) 119#define BRG_UART_CLK (BRG_INT_CLK/16) 120#define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16) 121 122void 123cpm_setbrg(uint brg, uint rate) 124{ 125 u32 __iomem *bp; 126 127 /* This is good enough to get SMCs running..... */ 128 bp = &cpmp->cp_brgc1; 129 bp += brg; 130 /* 131 * The BRG has a 12-bit counter. For really slow baud rates (or 132 * really fast processors), we may have to further divide by 16. 133 */ 134 if (((BRG_UART_CLK / rate) - 1) < 4096) 135 out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN); 136 else 137 out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) | 138 CPM_BRG_EN | CPM_BRG_DIV16); 139} 140EXPORT_SYMBOL(cpm_setbrg); 141 142struct cpm_ioport16 { 143 __be16 dir, par, odr_sor, dat, intr; 144 __be16 res[3]; 145}; 146 147struct cpm_ioport32b { 148 __be32 dir, par, odr, dat; 149}; 150 151struct cpm_ioport32e { 152 __be32 dir, par, sor, odr, dat; 153}; 154 155static void __init cpm1_set_pin32(int port, int pin, int flags) 156{ 157 struct cpm_ioport32e __iomem *iop; 158 pin = 1 << (31 - pin); 159 160 if (port == CPM_PORTB) 161 iop = (struct cpm_ioport32e __iomem *) 162 &mpc8xx_immr->im_cpm.cp_pbdir; 163 else 164 iop = (struct cpm_ioport32e __iomem *) 165 &mpc8xx_immr->im_cpm.cp_pedir; 166 167 if (flags & CPM_PIN_OUTPUT) 168 setbits32(&iop->dir, pin); 169 else 170 clrbits32(&iop->dir, pin); 171 172 if (!(flags & CPM_PIN_GPIO)) 173 setbits32(&iop->par, pin); 174 else 175 clrbits32(&iop->par, pin); 176 177 if (port == CPM_PORTB) { 178 if (flags & CPM_PIN_OPENDRAIN) 179 setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin); 180 else 181 clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin); 182 } 183 184 if (port == CPM_PORTE) { 185 if (flags & CPM_PIN_SECONDARY) 186 setbits32(&iop->sor, pin); 187 else 188 clrbits32(&iop->sor, pin); 189 190 if (flags & CPM_PIN_OPENDRAIN) 191 setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); 192 else 193 clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); 194 } 195} 196 197static void __init cpm1_set_pin16(int port, int pin, int flags) 198{ 199 struct cpm_ioport16 __iomem *iop = 200 (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport; 201 202 pin = 1 << (15 - pin); 203 204 if (port != 0) 205 iop += port - 1; 206 207 if (flags & CPM_PIN_OUTPUT) 208 setbits16(&iop->dir, pin); 209 else 210 clrbits16(&iop->dir, pin); 211 212 if (!(flags & CPM_PIN_GPIO)) 213 setbits16(&iop->par, pin); 214 else 215 clrbits16(&iop->par, pin); 216 217 if (port == CPM_PORTA) { 218 if (flags & CPM_PIN_OPENDRAIN) 219 setbits16(&iop->odr_sor, pin); 220 else 221 clrbits16(&iop->odr_sor, pin); 222 } 223 if (port == CPM_PORTC) { 224 if (flags & CPM_PIN_SECONDARY) 225 setbits16(&iop->odr_sor, pin); 226 else 227 clrbits16(&iop->odr_sor, pin); 228 if (flags & CPM_PIN_FALLEDGE) 229 setbits16(&iop->intr, pin); 230 else 231 clrbits16(&iop->intr, pin); 232 } 233} 234 235void __init cpm1_set_pin(enum cpm_port port, int pin, int flags) 236{ 237 if (port == CPM_PORTB || port == CPM_PORTE) 238 cpm1_set_pin32(port, pin, flags); 239 else 240 cpm1_set_pin16(port, pin, flags); 241} 242 243int __init cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode) 244{ 245 int shift; 246 int i, bits = 0; 247 u32 __iomem *reg; 248 u32 mask = 7; 249 250 u8 clk_map[][3] = { 251 {CPM_CLK_SCC1, CPM_BRG1, 0}, 252 {CPM_CLK_SCC1, CPM_BRG2, 1}, 253 {CPM_CLK_SCC1, CPM_BRG3, 2}, 254 {CPM_CLK_SCC1, CPM_BRG4, 3}, 255 {CPM_CLK_SCC1, CPM_CLK1, 4}, 256 {CPM_CLK_SCC1, CPM_CLK2, 5}, 257 {CPM_CLK_SCC1, CPM_CLK3, 6}, 258 {CPM_CLK_SCC1, CPM_CLK4, 7}, 259 260 {CPM_CLK_SCC2, CPM_BRG1, 0}, 261 {CPM_CLK_SCC2, CPM_BRG2, 1}, 262 {CPM_CLK_SCC2, CPM_BRG3, 2}, 263 {CPM_CLK_SCC2, CPM_BRG4, 3}, 264 {CPM_CLK_SCC2, CPM_CLK1, 4}, 265 {CPM_CLK_SCC2, CPM_CLK2, 5}, 266 {CPM_CLK_SCC2, CPM_CLK3, 6}, 267 {CPM_CLK_SCC2, CPM_CLK4, 7}, 268 269 {CPM_CLK_SCC3, CPM_BRG1, 0}, 270 {CPM_CLK_SCC3, CPM_BRG2, 1}, 271 {CPM_CLK_SCC3, CPM_BRG3, 2}, 272 {CPM_CLK_SCC3, CPM_BRG4, 3}, 273 {CPM_CLK_SCC3, CPM_CLK5, 4}, 274 {CPM_CLK_SCC3, CPM_CLK6, 5}, 275 {CPM_CLK_SCC3, CPM_CLK7, 6}, 276 {CPM_CLK_SCC3, CPM_CLK8, 7}, 277 278 {CPM_CLK_SCC4, CPM_BRG1, 0}, 279 {CPM_CLK_SCC4, CPM_BRG2, 1}, 280 {CPM_CLK_SCC4, CPM_BRG3, 2}, 281 {CPM_CLK_SCC4, CPM_BRG4, 3}, 282 {CPM_CLK_SCC4, CPM_CLK5, 4}, 283 {CPM_CLK_SCC4, CPM_CLK6, 5}, 284 {CPM_CLK_SCC4, CPM_CLK7, 6}, 285 {CPM_CLK_SCC4, CPM_CLK8, 7}, 286 287 {CPM_CLK_SMC1, CPM_BRG1, 0}, 288 {CPM_CLK_SMC1, CPM_BRG2, 1}, 289 {CPM_CLK_SMC1, CPM_BRG3, 2}, 290 {CPM_CLK_SMC1, CPM_BRG4, 3}, 291 {CPM_CLK_SMC1, CPM_CLK1, 4}, 292 {CPM_CLK_SMC1, CPM_CLK2, 5}, 293 {CPM_CLK_SMC1, CPM_CLK3, 6}, 294 {CPM_CLK_SMC1, CPM_CLK4, 7}, 295 296 {CPM_CLK_SMC2, CPM_BRG1, 0}, 297 {CPM_CLK_SMC2, CPM_BRG2, 1}, 298 {CPM_CLK_SMC2, CPM_BRG3, 2}, 299 {CPM_CLK_SMC2, CPM_BRG4, 3}, 300 {CPM_CLK_SMC2, CPM_CLK5, 4}, 301 {CPM_CLK_SMC2, CPM_CLK6, 5}, 302 {CPM_CLK_SMC2, CPM_CLK7, 6}, 303 {CPM_CLK_SMC2, CPM_CLK8, 7}, 304 }; 305 306 switch (target) { 307 case CPM_CLK_SCC1: 308 reg = &mpc8xx_immr->im_cpm.cp_sicr; 309 shift = 0; 310 break; 311 312 case CPM_CLK_SCC2: 313 reg = &mpc8xx_immr->im_cpm.cp_sicr; 314 shift = 8; 315 break; 316 317 case CPM_CLK_SCC3: 318 reg = &mpc8xx_immr->im_cpm.cp_sicr; 319 shift = 16; 320 break; 321 322 case CPM_CLK_SCC4: 323 reg = &mpc8xx_immr->im_cpm.cp_sicr; 324 shift = 24; 325 break; 326 327 case CPM_CLK_SMC1: 328 reg = &mpc8xx_immr->im_cpm.cp_simode; 329 shift = 12; 330 break; 331 332 case CPM_CLK_SMC2: 333 reg = &mpc8xx_immr->im_cpm.cp_simode; 334 shift = 28; 335 break; 336 337 default: 338 printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n"); 339 return -EINVAL; 340 } 341 342 for (i = 0; i < ARRAY_SIZE(clk_map); i++) { 343 if (clk_map[i][0] == target && clk_map[i][1] == clock) { 344 bits = clk_map[i][2]; 345 break; 346 } 347 } 348 349 if (i == ARRAY_SIZE(clk_map)) { 350 printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n"); 351 return -EINVAL; 352 } 353 354 bits <<= shift; 355 mask <<= shift; 356 357 if (reg == &mpc8xx_immr->im_cpm.cp_sicr) { 358 if (mode == CPM_CLK_RTX) { 359 bits |= bits << 3; 360 mask |= mask << 3; 361 } else if (mode == CPM_CLK_RX) { 362 bits <<= 3; 363 mask <<= 3; 364 } 365 } 366 367 out_be32(reg, (in_be32(reg) & ~mask) | bits); 368 369 return 0; 370} 371 372/* 373 * GPIO LIB API implementation 374 */ 375#ifdef CONFIG_8xx_GPIO 376 377struct cpm1_gpio16_chip { 378 struct of_mm_gpio_chip mm_gc; 379 spinlock_t lock; 380 381 /* shadowed data register to clear/set bits safely */ 382 u16 cpdata; 383 384 /* IRQ associated with Pins when relevant */ 385 int irq[16]; 386}; 387 388static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc) 389{ 390 struct cpm1_gpio16_chip *cpm1_gc = 391 container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc); 392 struct cpm_ioport16 __iomem *iop = mm_gc->regs; 393 394 cpm1_gc->cpdata = in_be16(&iop->dat); 395} 396 397static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio) 398{ 399 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 400 struct cpm_ioport16 __iomem *iop = mm_gc->regs; 401 u16 pin_mask; 402 403 pin_mask = 1 << (15 - gpio); 404 405 return !!(in_be16(&iop->dat) & pin_mask); 406} 407 408static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask, 409 int value) 410{ 411 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 412 struct cpm_ioport16 __iomem *iop = mm_gc->regs; 413 414 if (value) 415 cpm1_gc->cpdata |= pin_mask; 416 else 417 cpm1_gc->cpdata &= ~pin_mask; 418 419 out_be16(&iop->dat, cpm1_gc->cpdata); 420} 421 422static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value) 423{ 424 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 425 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 426 unsigned long flags; 427 u16 pin_mask = 1 << (15 - gpio); 428 429 spin_lock_irqsave(&cpm1_gc->lock, flags); 430 431 __cpm1_gpio16_set(mm_gc, pin_mask, value); 432 433 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 434} 435 436static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio) 437{ 438 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 439 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 440 441 return cpm1_gc->irq[gpio] ? : -ENXIO; 442} 443 444static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 445{ 446 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 447 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 448 struct cpm_ioport16 __iomem *iop = mm_gc->regs; 449 unsigned long flags; 450 u16 pin_mask = 1 << (15 - gpio); 451 452 spin_lock_irqsave(&cpm1_gc->lock, flags); 453 454 setbits16(&iop->dir, pin_mask); 455 __cpm1_gpio16_set(mm_gc, pin_mask, val); 456 457 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 458 459 return 0; 460} 461 462static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio) 463{ 464 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 465 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 466 struct cpm_ioport16 __iomem *iop = mm_gc->regs; 467 unsigned long flags; 468 u16 pin_mask = 1 << (15 - gpio); 469 470 spin_lock_irqsave(&cpm1_gc->lock, flags); 471 472 clrbits16(&iop->dir, pin_mask); 473 474 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 475 476 return 0; 477} 478 479int cpm1_gpiochip_add16(struct device *dev) 480{ 481 struct device_node *np = dev->of_node; 482 struct cpm1_gpio16_chip *cpm1_gc; 483 struct of_mm_gpio_chip *mm_gc; 484 struct gpio_chip *gc; 485 u16 mask; 486 487 cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL); 488 if (!cpm1_gc) 489 return -ENOMEM; 490 491 spin_lock_init(&cpm1_gc->lock); 492 493 if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) { 494 int i, j; 495 496 for (i = 0, j = 0; i < 16; i++) 497 if (mask & (1 << (15 - i))) 498 cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++); 499 } 500 501 mm_gc = &cpm1_gc->mm_gc; 502 gc = &mm_gc->gc; 503 504 mm_gc->save_regs = cpm1_gpio16_save_regs; 505 gc->ngpio = 16; 506 gc->direction_input = cpm1_gpio16_dir_in; 507 gc->direction_output = cpm1_gpio16_dir_out; 508 gc->get = cpm1_gpio16_get; 509 gc->set = cpm1_gpio16_set; 510 gc->to_irq = cpm1_gpio16_to_irq; 511 gc->parent = dev; 512 gc->owner = THIS_MODULE; 513 514 return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc); 515} 516 517struct cpm1_gpio32_chip { 518 struct of_mm_gpio_chip mm_gc; 519 spinlock_t lock; 520 521 /* shadowed data register to clear/set bits safely */ 522 u32 cpdata; 523}; 524 525static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc) 526{ 527 struct cpm1_gpio32_chip *cpm1_gc = 528 container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc); 529 struct cpm_ioport32b __iomem *iop = mm_gc->regs; 530 531 cpm1_gc->cpdata = in_be32(&iop->dat); 532} 533 534static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio) 535{ 536 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 537 struct cpm_ioport32b __iomem *iop = mm_gc->regs; 538 u32 pin_mask; 539 540 pin_mask = 1 << (31 - gpio); 541 542 return !!(in_be32(&iop->dat) & pin_mask); 543} 544 545static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, 546 int value) 547{ 548 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 549 struct cpm_ioport32b __iomem *iop = mm_gc->regs; 550 551 if (value) 552 cpm1_gc->cpdata |= pin_mask; 553 else 554 cpm1_gc->cpdata &= ~pin_mask; 555 556 out_be32(&iop->dat, cpm1_gc->cpdata); 557} 558 559static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value) 560{ 561 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 562 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 563 unsigned long flags; 564 u32 pin_mask = 1 << (31 - gpio); 565 566 spin_lock_irqsave(&cpm1_gc->lock, flags); 567 568 __cpm1_gpio32_set(mm_gc, pin_mask, value); 569 570 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 571} 572 573static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 574{ 575 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 576 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 577 struct cpm_ioport32b __iomem *iop = mm_gc->regs; 578 unsigned long flags; 579 u32 pin_mask = 1 << (31 - gpio); 580 581 spin_lock_irqsave(&cpm1_gc->lock, flags); 582 583 setbits32(&iop->dir, pin_mask); 584 __cpm1_gpio32_set(mm_gc, pin_mask, val); 585 586 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 587 588 return 0; 589} 590 591static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) 592{ 593 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 594 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 595 struct cpm_ioport32b __iomem *iop = mm_gc->regs; 596 unsigned long flags; 597 u32 pin_mask = 1 << (31 - gpio); 598 599 spin_lock_irqsave(&cpm1_gc->lock, flags); 600 601 clrbits32(&iop->dir, pin_mask); 602 603 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 604 605 return 0; 606} 607 608int cpm1_gpiochip_add32(struct device *dev) 609{ 610 struct device_node *np = dev->of_node; 611 struct cpm1_gpio32_chip *cpm1_gc; 612 struct of_mm_gpio_chip *mm_gc; 613 struct gpio_chip *gc; 614 615 cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL); 616 if (!cpm1_gc) 617 return -ENOMEM; 618 619 spin_lock_init(&cpm1_gc->lock); 620 621 mm_gc = &cpm1_gc->mm_gc; 622 gc = &mm_gc->gc; 623 624 mm_gc->save_regs = cpm1_gpio32_save_regs; 625 gc->ngpio = 32; 626 gc->direction_input = cpm1_gpio32_dir_in; 627 gc->direction_output = cpm1_gpio32_dir_out; 628 gc->get = cpm1_gpio32_get; 629 gc->set = cpm1_gpio32_set; 630 gc->parent = dev; 631 gc->owner = THIS_MODULE; 632 633 return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc); 634} 635 636#endif /* CONFIG_8xx_GPIO */ 637