162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation 462306a36Sopenharmony_ci * Rewrite, cleanup: 562306a36Sopenharmony_ci * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci#ifndef _ASM_POWERPC_TCE_H 962306a36Sopenharmony_ci#define _ASM_POWERPC_TCE_H 1062306a36Sopenharmony_ci#ifdef __KERNEL__ 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci#include <asm/iommu.h> 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci/* 1562306a36Sopenharmony_ci * Tces come in two formats, one for the virtual bus and a different 1662306a36Sopenharmony_ci * format for PCI. PCI TCEs can have hardware or software maintianed 1762306a36Sopenharmony_ci * coherency. 1862306a36Sopenharmony_ci */ 1962306a36Sopenharmony_ci#define TCE_VB 0 2062306a36Sopenharmony_ci#define TCE_PCI 1 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci#define TCE_ENTRY_SIZE 8 /* each TCE is 64 bits */ 2362306a36Sopenharmony_ci#define TCE_VALID 0x800 /* TCE valid */ 2462306a36Sopenharmony_ci#define TCE_ALLIO 0x400 /* TCE valid for all lpars */ 2562306a36Sopenharmony_ci#define TCE_PCI_WRITE 0x2 /* write from PCI allowed */ 2662306a36Sopenharmony_ci#define TCE_PCI_READ 0x1 /* read from PCI allowed */ 2762306a36Sopenharmony_ci#define TCE_VB_WRITE 0x1 /* write from VB allowed */ 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci#endif /* __KERNEL__ */ 3062306a36Sopenharmony_ci#endif /* _ASM_POWERPC_TCE_H */ 31