1/* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4#ifndef _ASM_POWERPC_PPC_ASM_H 5#define _ASM_POWERPC_PPC_ASM_H 6 7#include <linux/stringify.h> 8#include <asm/asm-compat.h> 9#include <asm/processor.h> 10#include <asm/ppc-opcode.h> 11#include <asm/firmware.h> 12#include <asm/feature-fixups.h> 13#include <asm/extable.h> 14 15#ifdef __ASSEMBLY__ 16 17#define SZL (BITS_PER_LONG/8) 18 19/* 20 * This expands to a sequence of operations with reg incrementing from 21 * start to end inclusive, of this form: 22 * 23 * op reg, (offset + (width * reg))(base) 24 * 25 * Note that offset is not the offset of the first operation unless start 26 * is zero (or width is zero). 27 */ 28.macro OP_REGS op, width, start, end, base, offset 29 .Lreg=\start 30 .rept (\end - \start + 1) 31 \op .Lreg, \offset + \width * .Lreg(\base) 32 .Lreg=.Lreg+1 33 .endr 34.endm 35 36/* 37 * This expands to a sequence of register clears for regs start to end 38 * inclusive, of the form: 39 * 40 * li rN, 0 41 */ 42.macro ZEROIZE_REGS start, end 43 .Lreg=\start 44 .rept (\end - \start + 1) 45 li .Lreg, 0 46 .Lreg=.Lreg+1 47 .endr 48.endm 49 50/* 51 * Macros for storing registers into and loading registers from 52 * exception frames. 53 */ 54#ifdef __powerpc64__ 55#define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, GPR0 56#define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, GPR0 57#define SAVE_NVGPRS(base) SAVE_GPRS(14, 31, base) 58#define REST_NVGPRS(base) REST_GPRS(14, 31, base) 59#else 60#define SAVE_GPRS(start, end, base) OP_REGS stw, 4, start, end, base, GPR0 61#define REST_GPRS(start, end, base) OP_REGS lwz, 4, start, end, base, GPR0 62#define SAVE_NVGPRS(base) SAVE_GPRS(13, 31, base) 63#define REST_NVGPRS(base) REST_GPRS(13, 31, base) 64#endif 65 66#define ZEROIZE_GPRS(start, end) ZEROIZE_REGS start, end 67#ifdef __powerpc64__ 68#define ZEROIZE_NVGPRS() ZEROIZE_GPRS(14, 31) 69#else 70#define ZEROIZE_NVGPRS() ZEROIZE_GPRS(13, 31) 71#endif 72#define ZEROIZE_GPR(n) ZEROIZE_GPRS(n, n) 73 74#define SAVE_GPR(n, base) SAVE_GPRS(n, n, base) 75#define REST_GPR(n, base) REST_GPRS(n, n, base) 76 77/* macros for handling user register sanitisation */ 78#ifdef CONFIG_INTERRUPT_SANITIZE_REGISTERS 79#define SANITIZE_SYSCALL_GPRS() ZEROIZE_GPR(0); \ 80 ZEROIZE_GPRS(5, 12); \ 81 ZEROIZE_NVGPRS() 82#define SANITIZE_GPR(n) ZEROIZE_GPR(n) 83#define SANITIZE_GPRS(start, end) ZEROIZE_GPRS(start, end) 84#define SANITIZE_NVGPRS() ZEROIZE_NVGPRS() 85#define SANITIZE_RESTORE_NVGPRS() REST_NVGPRS(r1) 86#define HANDLER_RESTORE_NVGPRS() 87#else 88#define SANITIZE_SYSCALL_GPRS() 89#define SANITIZE_GPR(n) 90#define SANITIZE_GPRS(start, end) 91#define SANITIZE_NVGPRS() 92#define SANITIZE_RESTORE_NVGPRS() 93#define HANDLER_RESTORE_NVGPRS() REST_NVGPRS(r1) 94#endif /* CONFIG_INTERRUPT_SANITIZE_REGISTERS */ 95 96#define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base) 97#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 98#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 99#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 100#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 101#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 102#define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base) 103#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 104#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 105#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 106#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 107#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 108 109#define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b 110#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 111#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 112#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 113#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 114#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 115#define REST_VR(n,b,base) li b,16*(n); lvx n,base,b 116#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 117#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 118#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 119#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 120#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 121 122#ifdef __BIG_ENDIAN__ 123#define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base) 124#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base) 125#else 126#define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \ 127 STXVD2X(n,b,base); \ 128 XXSWAPD(n,n) 129 130#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \ 131 XXSWAPD(n,n) 132#endif 133/* Save the lower 32 VSRs in the thread VSR region */ 134#define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b) 135#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 136#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 137#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 138#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 139#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 140#define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b) 141#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 142#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 143#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 144#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 145#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 146 147/* 148 * b = base register for addressing, o = base offset from register of 1st EVR 149 * n = first EVR, s = scratch 150 */ 151#define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) 152#define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) 153#define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) 154#define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) 155#define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) 156#define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) 157#define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n 158#define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) 159#define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) 160#define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) 161#define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) 162#define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) 163 164/* Macros to adjust thread priority for hardware multithreading */ 165#define HMT_VERY_LOW or 31,31,31 # very low priority 166#define HMT_LOW or 1,1,1 167#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 168#define HMT_MEDIUM or 2,2,2 169#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 170#define HMT_HIGH or 3,3,3 171#define HMT_EXTRA_HIGH or 7,7,7 # power7 only 172 173#ifdef CONFIG_PPC64 174#define ULONG_SIZE 8 175#else 176#define ULONG_SIZE 4 177#endif 178#define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) 179#define VCPU_GPR(n) __VCPU_GPR(__REG_##n) 180 181#ifdef __KERNEL__ 182 183/* 184 * Used to name C functions called from asm 185 */ 186#ifdef CONFIG_PPC_KERNEL_PCREL 187#define CFUNC(name) name@notoc 188#else 189#define CFUNC(name) name 190#endif 191 192/* 193 * We use __powerpc64__ here because we want the compat VDSO to use the 32-bit 194 * version below in the else case of the ifdef. 195 */ 196#ifdef __powerpc64__ 197 198#define STACKFRAMESIZE 256 199#define __STK_REG(i) (112 + ((i)-14)*8) 200#define STK_REG(i) __STK_REG(__REG_##i) 201 202#ifdef CONFIG_PPC64_ELF_ABI_V2 203#define STK_GOT 24 204#define __STK_PARAM(i) (32 + ((i)-3)*8) 205#else 206#define STK_GOT 40 207#define __STK_PARAM(i) (48 + ((i)-3)*8) 208#endif 209#define STK_PARAM(i) __STK_PARAM(__REG_##i) 210 211#ifdef CONFIG_PPC64_ELF_ABI_V2 212 213#define _GLOBAL(name) \ 214 .align 2 ; \ 215 .type name,@function; \ 216 .globl name; \ 217name: 218 219#ifdef CONFIG_PPC_KERNEL_PCREL 220#define _GLOBAL_TOC _GLOBAL 221#else 222#define _GLOBAL_TOC(name) \ 223 .align 2 ; \ 224 .type name,@function; \ 225 .globl name; \ 226name: \ 2270: addis r2,r12,(.TOC.-0b)@ha; \ 228 addi r2,r2,(.TOC.-0b)@l; \ 229 .localentry name,.-name 230#endif 231 232#define DOTSYM(a) a 233 234#else 235 236#define XGLUE(a,b) a##b 237#define GLUE(a,b) XGLUE(a,b) 238 239#define _GLOBAL(name) \ 240 .align 2 ; \ 241 .globl name; \ 242 .globl GLUE(.,name); \ 243 .pushsection ".opd","aw"; \ 244name: \ 245 .quad GLUE(.,name); \ 246 .quad .TOC.@tocbase; \ 247 .quad 0; \ 248 .popsection; \ 249 .type GLUE(.,name),@function; \ 250GLUE(.,name): 251 252#define _GLOBAL_TOC(name) _GLOBAL(name) 253 254#define DOTSYM(a) GLUE(.,a) 255 256#endif 257 258#else /* 32-bit */ 259 260#define _GLOBAL(n) \ 261 .globl n; \ 262n: 263 264#define _GLOBAL_TOC(name) _GLOBAL(name) 265 266#define DOTSYM(a) a 267 268#endif 269 270/* 271 * __kprobes (the C annotation) puts the symbol into the .kprobes.text 272 * section, which gets emitted at the end of regular text. 273 * 274 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to 275 * a blacklist. The former is for core kprobe functions/data, the 276 * latter is for those that incdentially must be excluded from probing 277 * and allows them to be linked at more optimal location within text. 278 */ 279#ifdef CONFIG_KPROBES 280#define _ASM_NOKPROBE_SYMBOL(entry) \ 281 .pushsection "_kprobe_blacklist","aw"; \ 282 PPC_LONG (entry) ; \ 283 .popsection 284#else 285#define _ASM_NOKPROBE_SYMBOL(entry) 286#endif 287 288#define FUNC_START(name) _GLOBAL(name) 289#define FUNC_END(name) 290 291/* 292 * LOAD_REG_IMMEDIATE(rn, expr) 293 * Loads the value of the constant expression 'expr' into register 'rn' 294 * using immediate instructions only. Use this when it's important not 295 * to reference other data (i.e. on ppc64 when the TOC pointer is not 296 * valid) and when 'expr' is a constant or absolute address. 297 * 298 * LOAD_REG_ADDR(rn, name) 299 * Loads the address of label 'name' into register 'rn'. Use this when 300 * you don't particularly need immediate instructions only, but you need 301 * the whole address in one register (e.g. it's a structure address and 302 * you want to access various offsets within it). On ppc32 this is 303 * identical to LOAD_REG_IMMEDIATE. 304 * 305 * LOAD_REG_ADDR_PIC(rn, name) 306 * Loads the address of label 'name' into register 'run'. Use this when 307 * the kernel doesn't run at the linked or relocated address. Please 308 * note that this macro will clobber the lr register. 309 * 310 * LOAD_REG_ADDRBASE(rn, name) 311 * ADDROFF(name) 312 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 313 * register 'rn'. ADDROFF(name) returns the remainder of the address as 314 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 315 * in size, so is suitable for use directly as an offset in load and store 316 * instructions. Use this when loading/storing a single word or less as: 317 * LOAD_REG_ADDRBASE(rX, name) 318 * ld rY,ADDROFF(name)(rX) 319 */ 320 321/* Be careful, this will clobber the lr register. */ 322#define LOAD_REG_ADDR_PIC(reg, name) \ 323 bcl 20,31,$+4; \ 3240: mflr reg; \ 325 addis reg,reg,(name - 0b)@ha; \ 326 addi reg,reg,(name - 0b)@l; 327 328#if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH) 329#define __AS_ATHIGH high 330#else 331#define __AS_ATHIGH h 332#endif 333 334.macro __LOAD_REG_IMMEDIATE_32 r, x 335 .if (\x) >= 0x8000 || (\x) < -0x8000 336 lis \r, (\x)@__AS_ATHIGH 337 .if (\x) & 0xffff != 0 338 ori \r, \r, (\x)@l 339 .endif 340 .else 341 li \r, (\x)@l 342 .endif 343.endm 344 345.macro __LOAD_REG_IMMEDIATE r, x 346 .if (\x) >= 0x80000000 || (\x) < -0x80000000 347 __LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32 348 sldi \r, \r, 32 349 .if (\x) & 0xffff0000 != 0 350 oris \r, \r, (\x)@__AS_ATHIGH 351 .endif 352 .if (\x) & 0xffff != 0 353 ori \r, \r, (\x)@l 354 .endif 355 .else 356 __LOAD_REG_IMMEDIATE_32 \r, \x 357 .endif 358.endm 359 360#ifdef __powerpc64__ 361 362#ifdef CONFIG_PPC_KERNEL_PCREL 363#define __LOAD_PACA_TOC(reg) \ 364 li reg,-1 365#else 366#define __LOAD_PACA_TOC(reg) \ 367 ld reg,PACATOC(r13) 368#endif 369 370#define LOAD_PACA_TOC() \ 371 __LOAD_PACA_TOC(r2) 372 373#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr 374 375#define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \ 376 lis tmp, (expr)@highest; \ 377 lis reg, (expr)@__AS_ATHIGH; \ 378 ori tmp, tmp, (expr)@higher; \ 379 ori reg, reg, (expr)@l; \ 380 rldimi reg, tmp, 32, 0 381 382#ifdef CONFIG_PPC_KERNEL_PCREL 383#define LOAD_REG_ADDR(reg,name) \ 384 pla reg,name@pcrel 385 386#else 387#define LOAD_REG_ADDR(reg,name) \ 388 addis reg,r2,name@toc@ha; \ 389 addi reg,reg,name@toc@l 390#endif 391 392#ifdef CONFIG_PPC_BOOK3E_64 393/* 394 * This is used in register-constrained interrupt handlers. Not to be used 395 * by BOOK3S. ld complains with "got/toc optimization is not supported" if r2 396 * is not used for the TOC offset, so use @got(tocreg). If the interrupt 397 * handlers saved r2 instead, LOAD_REG_ADDR could be used. 398 */ 399#define LOAD_REG_ADDR_ALTTOC(reg,tocreg,name) \ 400 ld reg,name@got(tocreg) 401#endif 402 403#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 404#define ADDROFF(name) 0 405 406/* offsets for stack frame layout */ 407#define LRSAVE 16 408 409/* 410 * GCC stack frames follow a different pattern on 32 vs 64. This can be used 411 * to make asm frames be consistent with C. 412 */ 413#define PPC_CREATE_STACK_FRAME(size) \ 414 mflr r0; \ 415 std r0,16(r1); \ 416 stdu r1,-(size)(r1) 417 418#else /* 32-bit */ 419 420#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr 421 422#define LOAD_REG_IMMEDIATE_SYM(reg,expr) \ 423 lis reg,(expr)@ha; \ 424 addi reg,reg,(expr)@l; 425 426#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name) 427 428#define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha 429#define ADDROFF(name) name@l 430 431/* offsets for stack frame layout */ 432#define LRSAVE 4 433 434#define PPC_CREATE_STACK_FRAME(size) \ 435 stwu r1,-(size)(r1); \ 436 mflr r0; \ 437 stw r0,(size+4)(r1) 438 439#endif 440 441/* various errata or part fixups */ 442#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_E500) 443#define MFTB(dest) \ 44490: mfspr dest, SPRN_TBRL; \ 445BEGIN_FTR_SECTION_NESTED(96); \ 446 cmpwi dest,0; \ 447 beq- 90b; \ 448END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 449#else 450#define MFTB(dest) MFTBL(dest) 451#endif 452 453#ifdef CONFIG_PPC_8xx 454#define MFTBL(dest) mftb dest 455#define MFTBU(dest) mftbu dest 456#else 457#define MFTBL(dest) mfspr dest, SPRN_TBRL 458#define MFTBU(dest) mfspr dest, SPRN_TBRU 459#endif 460 461#ifndef CONFIG_SMP 462#define TLBSYNC 463#else 464#define TLBSYNC tlbsync; sync 465#endif 466 467#ifdef CONFIG_PPC64 468#define MTOCRF(FXM, RS) \ 469 BEGIN_FTR_SECTION_NESTED(848); \ 470 mtcrf (FXM), RS; \ 471 FTR_SECTION_ELSE_NESTED(848); \ 472 mtocrf (FXM), RS; \ 473 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 474#endif 475 476/* 477 * This instruction is not implemented on the PPC 603 or 601; however, on 478 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 479 * All of these instructions exist in the 8xx, they have magical powers, 480 * and they must be used. 481 */ 482 483#if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx) 484#define tlbia \ 485 li r4,1024; \ 486 mtctr r4; \ 487 lis r4,KERNELBASE@h; \ 488 .machine push; \ 489 .machine "power4"; \ 4900: tlbie r4; \ 491 .machine pop; \ 492 addi r4,r4,0x1000; \ 493 bdnz 0b 494#endif 495 496 497#ifdef CONFIG_IBM440EP_ERR42 498#define PPC440EP_ERR42 isync 499#else 500#define PPC440EP_ERR42 501#endif 502 503/* The following stops all load and store data streams associated with stream 504 * ID (ie. streams created explicitly). The embedded and server mnemonics for 505 * dcbt are different so this must only be used for server. 506 */ 507#define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \ 508 lis scratch,0x60000000@h; \ 509 dcbt 0,scratch,0b01010 510 511/* 512 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 513 * keep the address intact to be compatible with code shared with 514 * 32-bit classic. 515 * 516 * On the other hand, I find it useful to have them behave as expected 517 * by their name (ie always do the addition) on 64-bit BookE 518 */ 519#if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 520#define toreal(rd) 521#define fromreal(rd) 522 523/* 524 * We use addis to ensure compatibility with the "classic" ppc versions of 525 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 526 * converting the address in r0, and so this version has to do that too 527 * (i.e. set register rd to 0 when rs == 0). 528 */ 529#define tophys(rd,rs) \ 530 addis rd,rs,0 531 532#define tovirt(rd,rs) \ 533 addis rd,rs,0 534 535#elif defined(CONFIG_PPC64) 536#define toreal(rd) /* we can access c000... in real mode */ 537#define fromreal(rd) 538 539#define tophys(rd,rs) \ 540 clrldi rd,rs,2 541 542#define tovirt(rd,rs) \ 543 rotldi rd,rs,16; \ 544 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 545 rotldi rd,rd,48 546#else 547#define toreal(rd) tophys(rd,rd) 548#define fromreal(rd) tovirt(rd,rd) 549 550#define tophys(rd, rs) addis rd, rs, -PAGE_OFFSET@h 551#define tovirt(rd, rs) addis rd, rs, PAGE_OFFSET@h 552#endif 553 554#ifdef CONFIG_PPC_BOOK3S_64 555#define MTMSRD(r) mtmsrd r 556#define MTMSR_EERI(reg) mtmsrd reg,1 557#else 558#define MTMSRD(r) mtmsr r 559#define MTMSR_EERI(reg) mtmsr reg 560#endif 561 562#endif /* __KERNEL__ */ 563 564/* The boring bits... */ 565 566/* Condition Register Bit Fields */ 567 568#define cr0 0 569#define cr1 1 570#define cr2 2 571#define cr3 3 572#define cr4 4 573#define cr5 5 574#define cr6 6 575#define cr7 7 576 577 578/* 579 * General Purpose Registers (GPRs) 580 * 581 * The lower case r0-r31 should be used in preference to the upper 582 * case R0-R31 as they provide more error checking in the assembler. 583 * Use R0-31 only when really nessesary. 584 */ 585 586#define r0 %r0 587#define r1 %r1 588#define r2 %r2 589#define r3 %r3 590#define r4 %r4 591#define r5 %r5 592#define r6 %r6 593#define r7 %r7 594#define r8 %r8 595#define r9 %r9 596#define r10 %r10 597#define r11 %r11 598#define r12 %r12 599#define r13 %r13 600#define r14 %r14 601#define r15 %r15 602#define r16 %r16 603#define r17 %r17 604#define r18 %r18 605#define r19 %r19 606#define r20 %r20 607#define r21 %r21 608#define r22 %r22 609#define r23 %r23 610#define r24 %r24 611#define r25 %r25 612#define r26 %r26 613#define r27 %r27 614#define r28 %r28 615#define r29 %r29 616#define r30 %r30 617#define r31 %r31 618 619 620/* Floating Point Registers (FPRs) */ 621 622#define fr0 0 623#define fr1 1 624#define fr2 2 625#define fr3 3 626#define fr4 4 627#define fr5 5 628#define fr6 6 629#define fr7 7 630#define fr8 8 631#define fr9 9 632#define fr10 10 633#define fr11 11 634#define fr12 12 635#define fr13 13 636#define fr14 14 637#define fr15 15 638#define fr16 16 639#define fr17 17 640#define fr18 18 641#define fr19 19 642#define fr20 20 643#define fr21 21 644#define fr22 22 645#define fr23 23 646#define fr24 24 647#define fr25 25 648#define fr26 26 649#define fr27 27 650#define fr28 28 651#define fr29 29 652#define fr30 30 653#define fr31 31 654 655/* AltiVec Registers (VPRs) */ 656 657#define v0 0 658#define v1 1 659#define v2 2 660#define v3 3 661#define v4 4 662#define v5 5 663#define v6 6 664#define v7 7 665#define v8 8 666#define v9 9 667#define v10 10 668#define v11 11 669#define v12 12 670#define v13 13 671#define v14 14 672#define v15 15 673#define v16 16 674#define v17 17 675#define v18 18 676#define v19 19 677#define v20 20 678#define v21 21 679#define v22 22 680#define v23 23 681#define v24 24 682#define v25 25 683#define v26 26 684#define v27 27 685#define v28 28 686#define v29 29 687#define v30 30 688#define v31 31 689 690/* VSX Registers (VSRs) */ 691 692#define vs0 0 693#define vs1 1 694#define vs2 2 695#define vs3 3 696#define vs4 4 697#define vs5 5 698#define vs6 6 699#define vs7 7 700#define vs8 8 701#define vs9 9 702#define vs10 10 703#define vs11 11 704#define vs12 12 705#define vs13 13 706#define vs14 14 707#define vs15 15 708#define vs16 16 709#define vs17 17 710#define vs18 18 711#define vs19 19 712#define vs20 20 713#define vs21 21 714#define vs22 22 715#define vs23 23 716#define vs24 24 717#define vs25 25 718#define vs26 26 719#define vs27 27 720#define vs28 28 721#define vs29 29 722#define vs30 30 723#define vs31 31 724#define vs32 32 725#define vs33 33 726#define vs34 34 727#define vs35 35 728#define vs36 36 729#define vs37 37 730#define vs38 38 731#define vs39 39 732#define vs40 40 733#define vs41 41 734#define vs42 42 735#define vs43 43 736#define vs44 44 737#define vs45 45 738#define vs46 46 739#define vs47 47 740#define vs48 48 741#define vs49 49 742#define vs50 50 743#define vs51 51 744#define vs52 52 745#define vs53 53 746#define vs54 54 747#define vs55 55 748#define vs56 56 749#define vs57 57 750#define vs58 58 751#define vs59 59 752#define vs60 60 753#define vs61 61 754#define vs62 62 755#define vs63 63 756 757/* SPE Registers (EVPRs) */ 758 759#define evr0 0 760#define evr1 1 761#define evr2 2 762#define evr3 3 763#define evr4 4 764#define evr5 5 765#define evr6 6 766#define evr7 7 767#define evr8 8 768#define evr9 9 769#define evr10 10 770#define evr11 11 771#define evr12 12 772#define evr13 13 773#define evr14 14 774#define evr15 15 775#define evr16 16 776#define evr17 17 777#define evr18 18 778#define evr19 19 779#define evr20 20 780#define evr21 21 781#define evr22 22 782#define evr23 23 783#define evr24 24 784#define evr25 25 785#define evr26 26 786#define evr27 27 787#define evr28 28 788#define evr29 29 789#define evr30 30 790#define evr31 31 791 792#define RFSCV .long 0x4c0000a4 793 794/* 795 * Create an endian fixup trampoline 796 * 797 * This starts with a "tdi 0,0,0x48" instruction which is 798 * essentially a "trap never", and thus akin to a nop. 799 * 800 * The opcode for this instruction read with the wrong endian 801 * however results in a b . + 8 802 * 803 * So essentially we use that trick to execute the following 804 * trampoline in "reverse endian" if we are running with the 805 * MSR_LE bit set the "wrong" way for whatever endianness the 806 * kernel is built for. 807 */ 808 809#ifdef CONFIG_PPC_BOOK3E_64 810#define FIXUP_ENDIAN 811#else 812/* 813 * This version may be used in HV or non-HV context. 814 * MSR[EE] must be disabled. 815 */ 816#define FIXUP_ENDIAN \ 817 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 818 b 191f; /* Skip trampoline if endian is good */ \ 819 .long 0xa600607d; /* mfmsr r11 */ \ 820 .long 0x01006b69; /* xori r11,r11,1 */ \ 821 .long 0x00004039; /* li r10,0 */ \ 822 .long 0x6401417d; /* mtmsrd r10,1 */ \ 823 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 824 .long 0xa602487d; /* mflr r10 */ \ 825 .long 0x14004a39; /* addi r10,r10,20 */ \ 826 .long 0xa6035a7d; /* mtsrr0 r10 */ \ 827 .long 0xa6037b7d; /* mtsrr1 r11 */ \ 828 .long 0x2400004c; /* rfid */ \ 829191: 830 831/* 832 * This version that may only be used with MSR[HV]=1 833 * - Does not clear MSR[RI], so more robust. 834 * - Slightly smaller and faster. 835 */ 836#define FIXUP_ENDIAN_HV \ 837 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 838 b 191f; /* Skip trampoline if endian is good */ \ 839 .long 0xa600607d; /* mfmsr r11 */ \ 840 .long 0x01006b69; /* xori r11,r11,1 */ \ 841 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 842 .long 0xa602487d; /* mflr r10 */ \ 843 .long 0x14004a39; /* addi r10,r10,20 */ \ 844 .long 0xa64b5a7d; /* mthsrr0 r10 */ \ 845 .long 0xa64b7b7d; /* mthsrr1 r11 */ \ 846 .long 0x2402004c; /* hrfid */ \ 847191: 848 849#endif /* !CONFIG_PPC_BOOK3E_64 */ 850 851#endif /* __ASSEMBLY__ */ 852 853#define SOFT_MASK_TABLE(_start, _end) \ 854 stringify_in_c(.section __soft_mask_table,"a";)\ 855 stringify_in_c(.balign 8;) \ 856 stringify_in_c(.llong (_start);) \ 857 stringify_in_c(.llong (_end);) \ 858 stringify_in_c(.previous) 859 860#define RESTART_TABLE(_start, _end, _target) \ 861 stringify_in_c(.section __restart_table,"a";)\ 862 stringify_in_c(.balign 8;) \ 863 stringify_in_c(.llong (_start);) \ 864 stringify_in_c(.llong (_end);) \ 865 stringify_in_c(.llong (_target);) \ 866 stringify_in_c(.previous) 867 868#ifdef CONFIG_PPC_E500 869#define BTB_FLUSH(reg) \ 870 lis reg,BUCSR_INIT@h; \ 871 ori reg,reg,BUCSR_INIT@l; \ 872 mtspr SPRN_BUCSR,reg; \ 873 isync; 874#else 875#define BTB_FLUSH(reg) 876#endif /* CONFIG_PPC_E500 */ 877 878#if defined(CONFIG_PPC64_ELF_ABI_V1) 879#define STACK_FRAME_PARAMS 48 880#elif defined(CONFIG_PPC64_ELF_ABI_V2) 881#define STACK_FRAME_PARAMS 32 882#elif defined(CONFIG_PPC32) 883#define STACK_FRAME_PARAMS 8 884#endif 885 886#endif /* _ASM_POWERPC_PPC_ASM_H */ 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