162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */
262306a36Sopenharmony_ci#ifndef _ASM_POWERPC_MMU_40X_H_
362306a36Sopenharmony_ci#define _ASM_POWERPC_MMU_40X_H_
462306a36Sopenharmony_ci
562306a36Sopenharmony_ci/*
662306a36Sopenharmony_ci * PPC40x support
762306a36Sopenharmony_ci */
862306a36Sopenharmony_ci
962306a36Sopenharmony_ci#define PPC40X_TLB_SIZE 64
1062306a36Sopenharmony_ci
1162306a36Sopenharmony_ci/*
1262306a36Sopenharmony_ci * TLB entries are defined by a "high" tag portion and a "low" data
1362306a36Sopenharmony_ci * portion.  On all architectures, the data portion is 32-bits.
1462306a36Sopenharmony_ci *
1562306a36Sopenharmony_ci * TLB entries are managed entirely under software control by reading,
1662306a36Sopenharmony_ci * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
1762306a36Sopenharmony_ci * instructions.
1862306a36Sopenharmony_ci */
1962306a36Sopenharmony_ci
2062306a36Sopenharmony_ci#define	TLB_LO          1
2162306a36Sopenharmony_ci#define	TLB_HI          0
2262306a36Sopenharmony_ci
2362306a36Sopenharmony_ci#define	TLB_DATA        TLB_LO
2462306a36Sopenharmony_ci#define	TLB_TAG         TLB_HI
2562306a36Sopenharmony_ci
2662306a36Sopenharmony_ci/* Tag portion */
2762306a36Sopenharmony_ci
2862306a36Sopenharmony_ci#define TLB_EPN_MASK    0xFFFFFC00      /* Effective Page Number */
2962306a36Sopenharmony_ci#define TLB_PAGESZ_MASK 0x00000380
3062306a36Sopenharmony_ci#define TLB_PAGESZ(x)   (((x) & 0x7) << 7)
3162306a36Sopenharmony_ci#define   PAGESZ_1K		0
3262306a36Sopenharmony_ci#define   PAGESZ_4K             1
3362306a36Sopenharmony_ci#define   PAGESZ_16K            2
3462306a36Sopenharmony_ci#define   PAGESZ_64K            3
3562306a36Sopenharmony_ci#define   PAGESZ_256K           4
3662306a36Sopenharmony_ci#define   PAGESZ_1M             5
3762306a36Sopenharmony_ci#define   PAGESZ_4M             6
3862306a36Sopenharmony_ci#define   PAGESZ_16M            7
3962306a36Sopenharmony_ci#define TLB_VALID       0x00000040      /* Entry is valid */
4062306a36Sopenharmony_ci
4162306a36Sopenharmony_ci/* Data portion */
4262306a36Sopenharmony_ci
4362306a36Sopenharmony_ci#define TLB_RPN_MASK    0xFFFFFC00      /* Real Page Number */
4462306a36Sopenharmony_ci#define TLB_PERM_MASK   0x00000300
4562306a36Sopenharmony_ci#define TLB_EX          0x00000200      /* Instruction execution allowed */
4662306a36Sopenharmony_ci#define TLB_WR          0x00000100      /* Writes permitted */
4762306a36Sopenharmony_ci#define TLB_ZSEL_MASK   0x000000F0
4862306a36Sopenharmony_ci#define TLB_ZSEL(x)     (((x) & 0xF) << 4)
4962306a36Sopenharmony_ci#define TLB_ATTR_MASK   0x0000000F
5062306a36Sopenharmony_ci#define TLB_W           0x00000008      /* Caching is write-through */
5162306a36Sopenharmony_ci#define TLB_I           0x00000004      /* Caching is inhibited */
5262306a36Sopenharmony_ci#define TLB_M           0x00000002      /* Memory is coherent */
5362306a36Sopenharmony_ci#define TLB_G           0x00000001      /* Memory is guarded from prefetch */
5462306a36Sopenharmony_ci
5562306a36Sopenharmony_ci#ifndef __ASSEMBLY__
5662306a36Sopenharmony_ci
5762306a36Sopenharmony_citypedef struct {
5862306a36Sopenharmony_ci	unsigned int	id;
5962306a36Sopenharmony_ci	unsigned int	active;
6062306a36Sopenharmony_ci	void __user	*vdso;
6162306a36Sopenharmony_ci} mm_context_t;
6262306a36Sopenharmony_ci
6362306a36Sopenharmony_ci#endif /* !__ASSEMBLY__ */
6462306a36Sopenharmony_ci
6562306a36Sopenharmony_ci#define mmu_virtual_psize	MMU_PAGE_4K
6662306a36Sopenharmony_ci#define mmu_linear_psize	MMU_PAGE_256M
6762306a36Sopenharmony_ci
6862306a36Sopenharmony_ci#endif /* _ASM_POWERPC_MMU_40X_H_ */
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