1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_POWERPC_MMU_H_
3#define _ASM_POWERPC_MMU_H_
4#ifdef __KERNEL__
5
6#include <linux/types.h>
7
8#include <asm/asm-const.h>
9
10/*
11 * MMU features bit definitions
12 */
13
14/*
15 * MMU families
16 */
17#define MMU_FTR_HPTE_TABLE		ASM_CONST(0x00000001)
18#define MMU_FTR_TYPE_8xx		ASM_CONST(0x00000002)
19#define MMU_FTR_TYPE_40x		ASM_CONST(0x00000004)
20#define MMU_FTR_TYPE_44x		ASM_CONST(0x00000008)
21#define MMU_FTR_TYPE_FSL_E		ASM_CONST(0x00000010)
22#define MMU_FTR_TYPE_47x		ASM_CONST(0x00000020)
23
24/* Radix page table supported and enabled */
25#define MMU_FTR_TYPE_RADIX		ASM_CONST(0x00000040)
26
27/*
28 * Individual features below.
29 */
30
31/*
32 * Supports KUAP feature
33 * key 0 controlling userspace addresses on radix
34 * Key 3 on hash
35 */
36#define MMU_FTR_KUAP		ASM_CONST(0x00000200)
37
38/*
39 * Supports KUEP feature
40 * key 0 controlling userspace addresses on radix
41 * Key 3 on hash
42 */
43#define MMU_FTR_BOOK3S_KUEP		ASM_CONST(0x00000400)
44
45/*
46 * Support for memory protection keys.
47 */
48#define MMU_FTR_PKEY			ASM_CONST(0x00000800)
49
50/* Guest Translation Shootdown Enable */
51#define MMU_FTR_GTSE			ASM_CONST(0x00001000)
52
53/*
54 * Support for 68 bit VA space. We added that from ISA 2.05
55 */
56#define MMU_FTR_68_BIT_VA		ASM_CONST(0x00002000)
57/*
58 * Kernel read only support.
59 * We added the ppp value 0b110 in ISA 2.04.
60 */
61#define MMU_FTR_KERNEL_RO		ASM_CONST(0x00004000)
62
63/*
64 * We need to clear top 16bits of va (from the remaining 64 bits )in
65 * tlbie* instructions
66 */
67#define MMU_FTR_TLBIE_CROP_VA		ASM_CONST(0x00008000)
68
69/* Enable use of high BAT registers */
70#define MMU_FTR_USE_HIGH_BATS		ASM_CONST(0x00010000)
71
72/* Enable >32-bit physical addresses on 32-bit processor, only used
73 * by CONFIG_PPC_BOOK3S_32 currently as BookE supports that from day 1
74 */
75#define MMU_FTR_BIG_PHYS		ASM_CONST(0x00020000)
76
77/* Enable use of broadcast TLB invalidations. We don't always set it
78 * on processors that support it due to other constraints with the
79 * use of such invalidations
80 */
81#define MMU_FTR_USE_TLBIVAX_BCAST	ASM_CONST(0x00040000)
82
83/* Enable use of tlbilx invalidate instructions.
84 */
85#define MMU_FTR_USE_TLBILX		ASM_CONST(0x00080000)
86
87/* This indicates that the processor cannot handle multiple outstanding
88 * broadcast tlbivax or tlbsync. This makes the code use a spinlock
89 * around such invalidate forms.
90 */
91#define MMU_FTR_LOCK_BCAST_INVAL	ASM_CONST(0x00100000)
92
93/* This indicates that the processor doesn't handle way selection
94 * properly and needs SW to track and update the LRU state.  This
95 * is specific to an errata on e300c2/c3/c4 class parts
96 */
97#define MMU_FTR_NEED_DTLB_SW_LRU	ASM_CONST(0x00200000)
98
99/* Doesn't support the B bit (1T segment) in SLBIE
100 */
101#define MMU_FTR_NO_SLBIE_B		ASM_CONST(0x02000000)
102
103/* Support 16M large pages
104 */
105#define MMU_FTR_16M_PAGE		ASM_CONST(0x04000000)
106
107/* Supports TLBIEL variant
108 */
109#define MMU_FTR_TLBIEL			ASM_CONST(0x08000000)
110
111/* Supports tlbies w/o locking
112 */
113#define MMU_FTR_LOCKLESS_TLBIE		ASM_CONST(0x10000000)
114
115/* Large pages can be marked CI
116 */
117#define MMU_FTR_CI_LARGE_PAGE		ASM_CONST(0x20000000)
118
119/* 1T segments available
120 */
121#define MMU_FTR_1T_SEGMENT		ASM_CONST(0x40000000)
122
123// NX paste RMA reject in DSI
124#define MMU_FTR_NX_DSI			ASM_CONST(0x80000000)
125
126/* MMU feature bit sets for various CPUs */
127#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2	(MMU_FTR_HPTE_TABLE | MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
128#define MMU_FTRS_POWER		MMU_FTRS_DEFAULT_HPTE_ARCH_V2
129#define MMU_FTRS_PPC970		MMU_FTRS_POWER | MMU_FTR_TLBIE_CROP_VA
130#define MMU_FTRS_POWER5		MMU_FTRS_POWER | MMU_FTR_LOCKLESS_TLBIE
131#define MMU_FTRS_POWER6		MMU_FTRS_POWER5 | MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA
132#define MMU_FTRS_POWER7		MMU_FTRS_POWER6
133#define MMU_FTRS_POWER8		MMU_FTRS_POWER6
134#define MMU_FTRS_POWER9		MMU_FTRS_POWER6
135#define MMU_FTRS_POWER10	MMU_FTRS_POWER6
136#define MMU_FTRS_CELL		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
137				MMU_FTR_CI_LARGE_PAGE
138#define MMU_FTRS_PA6T		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
139				MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
140#ifndef __ASSEMBLY__
141#include <linux/bug.h>
142#include <asm/cputable.h>
143#include <asm/page.h>
144
145typedef pte_t *pgtable_t;
146
147enum {
148	MMU_FTRS_POSSIBLE =
149#if defined(CONFIG_PPC_BOOK3S_604)
150		MMU_FTR_HPTE_TABLE |
151#endif
152#ifdef CONFIG_PPC_8xx
153		MMU_FTR_TYPE_8xx |
154#endif
155#ifdef CONFIG_40x
156		MMU_FTR_TYPE_40x |
157#endif
158#ifdef CONFIG_PPC_47x
159		MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL |
160#elif defined(CONFIG_44x)
161		MMU_FTR_TYPE_44x |
162#endif
163#ifdef CONFIG_PPC_E500
164		MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX |
165#endif
166#ifdef CONFIG_PPC_BOOK3S_32
167		MMU_FTR_USE_HIGH_BATS |
168#endif
169#ifdef CONFIG_PPC_83xx
170		MMU_FTR_NEED_DTLB_SW_LRU |
171#endif
172#ifdef CONFIG_PPC_BOOK3S_64
173		MMU_FTR_KERNEL_RO |
174#ifdef CONFIG_PPC_64S_HASH_MMU
175		MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
176		MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
177		MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
178		MMU_FTR_68_BIT_VA | MMU_FTR_HPTE_TABLE |
179#endif
180#ifdef CONFIG_PPC_RADIX_MMU
181		MMU_FTR_TYPE_RADIX |
182		MMU_FTR_GTSE | MMU_FTR_NX_DSI |
183#endif /* CONFIG_PPC_RADIX_MMU */
184#endif
185#ifdef CONFIG_PPC_KUAP
186	MMU_FTR_KUAP |
187#endif /* CONFIG_PPC_KUAP */
188#ifdef CONFIG_PPC_MEM_KEYS
189	MMU_FTR_PKEY |
190#endif
191#ifdef CONFIG_PPC_KUEP
192	MMU_FTR_BOOK3S_KUEP |
193#endif /* CONFIG_PPC_KUAP */
194
195		0,
196};
197
198#if defined(CONFIG_PPC_BOOK3S_604) && !defined(CONFIG_PPC_BOOK3S_603)
199#define MMU_FTRS_ALWAYS		MMU_FTR_HPTE_TABLE
200#endif
201#ifdef CONFIG_PPC_8xx
202#define MMU_FTRS_ALWAYS		MMU_FTR_TYPE_8xx
203#endif
204#ifdef CONFIG_40x
205#define MMU_FTRS_ALWAYS		MMU_FTR_TYPE_40x
206#endif
207#ifdef CONFIG_PPC_47x
208#define MMU_FTRS_ALWAYS		MMU_FTR_TYPE_47x
209#elif defined(CONFIG_44x)
210#define MMU_FTRS_ALWAYS		MMU_FTR_TYPE_44x
211#endif
212#ifdef CONFIG_PPC_E500
213#define MMU_FTRS_ALWAYS		MMU_FTR_TYPE_FSL_E
214#endif
215
216/* BOOK3S_64 options */
217#if defined(CONFIG_PPC_RADIX_MMU) && !defined(CONFIG_PPC_64S_HASH_MMU)
218#define MMU_FTRS_ALWAYS		MMU_FTR_TYPE_RADIX
219#elif !defined(CONFIG_PPC_RADIX_MMU) && defined(CONFIG_PPC_64S_HASH_MMU)
220#define MMU_FTRS_ALWAYS		MMU_FTR_HPTE_TABLE
221#endif
222
223#ifndef MMU_FTRS_ALWAYS
224#define MMU_FTRS_ALWAYS		0
225#endif
226
227static __always_inline bool early_mmu_has_feature(unsigned long feature)
228{
229	if (MMU_FTRS_ALWAYS & feature)
230		return true;
231
232	return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature);
233}
234
235#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
236#include <linux/jump_label.h>
237
238#define NUM_MMU_FTR_KEYS	32
239
240extern struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS];
241
242extern void mmu_feature_keys_init(void);
243
244static __always_inline bool mmu_has_feature(unsigned long feature)
245{
246	int i;
247
248#ifndef __clang__ /* clang can't cope with this */
249	BUILD_BUG_ON(!__builtin_constant_p(feature));
250#endif
251
252#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG
253	if (!static_key_initialized) {
254		printk("Warning! mmu_has_feature() used prior to jump label init!\n");
255		dump_stack();
256		return early_mmu_has_feature(feature);
257	}
258#endif
259
260	if (MMU_FTRS_ALWAYS & feature)
261		return true;
262
263	if (!(MMU_FTRS_POSSIBLE & feature))
264		return false;
265
266	i = __builtin_ctzl(feature);
267	return static_branch_likely(&mmu_feature_keys[i]);
268}
269
270static inline void mmu_clear_feature(unsigned long feature)
271{
272	int i;
273
274	i = __builtin_ctzl(feature);
275	cur_cpu_spec->mmu_features &= ~feature;
276	static_branch_disable(&mmu_feature_keys[i]);
277}
278#else
279
280static inline void mmu_feature_keys_init(void)
281{
282
283}
284
285static __always_inline bool mmu_has_feature(unsigned long feature)
286{
287	return early_mmu_has_feature(feature);
288}
289
290static inline void mmu_clear_feature(unsigned long feature)
291{
292	cur_cpu_spec->mmu_features &= ~feature;
293}
294#endif /* CONFIG_JUMP_LABEL */
295
296extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
297
298#ifdef CONFIG_PPC64
299/* This is our real memory area size on ppc64 server, on embedded, we
300 * make it match the size our of bolted TLB area
301 */
302extern u64 ppc64_rma_size;
303
304/* Cleanup function used by kexec */
305extern void mmu_cleanup_all(void);
306extern void radix__mmu_cleanup_all(void);
307
308/* Functions for creating and updating partition table on POWER9 */
309extern void mmu_partition_table_init(void);
310extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
311					  unsigned long dw1, bool flush);
312#endif /* CONFIG_PPC64 */
313
314struct mm_struct;
315#ifdef CONFIG_DEBUG_VM
316extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
317#else /* CONFIG_DEBUG_VM */
318static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
319{
320}
321#endif /* !CONFIG_DEBUG_VM */
322
323static __always_inline bool radix_enabled(void)
324{
325	return mmu_has_feature(MMU_FTR_TYPE_RADIX);
326}
327
328static __always_inline bool early_radix_enabled(void)
329{
330	return early_mmu_has_feature(MMU_FTR_TYPE_RADIX);
331}
332
333#ifdef CONFIG_STRICT_KERNEL_RWX
334static inline bool strict_kernel_rwx_enabled(void)
335{
336	return rodata_enabled;
337}
338#else
339static inline bool strict_kernel_rwx_enabled(void)
340{
341	return false;
342}
343#endif
344
345static inline bool strict_module_rwx_enabled(void)
346{
347	return IS_ENABLED(CONFIG_STRICT_MODULE_RWX) && strict_kernel_rwx_enabled();
348}
349#endif /* !__ASSEMBLY__ */
350
351/* The kernel use the constants below to index in the page sizes array.
352 * The use of fixed constants for this purpose is better for performances
353 * of the low level hash refill handlers.
354 *
355 * A non supported page size has a "shift" field set to 0
356 *
357 * Any new page size being implemented can get a new entry in here. Whether
358 * the kernel will use it or not is a different matter though. The actual page
359 * size used by hugetlbfs is not defined here and may be made variable
360 *
361 * Note: This array ended up being a false good idea as it's growing to the
362 * point where I wonder if we should replace it with something different,
363 * to think about, feedback welcome. --BenH.
364 */
365
366/* These are #defines as they have to be used in assembly */
367#define MMU_PAGE_4K	0
368#define MMU_PAGE_16K	1
369#define MMU_PAGE_64K	2
370#define MMU_PAGE_64K_AP	3	/* "Admixed pages" (hash64 only) */
371#define MMU_PAGE_256K	4
372#define MMU_PAGE_512K	5
373#define MMU_PAGE_1M	6
374#define MMU_PAGE_2M	7
375#define MMU_PAGE_4M	8
376#define MMU_PAGE_8M	9
377#define MMU_PAGE_16M	10
378#define MMU_PAGE_64M	11
379#define MMU_PAGE_256M	12
380#define MMU_PAGE_1G	13
381#define MMU_PAGE_16G	14
382#define MMU_PAGE_64G	15
383
384/*
385 * N.B. we need to change the type of hpte_page_sizes if this gets to be > 16
386 * Also we need to change he type of mm_context.low/high_slices_psize.
387 */
388#define MMU_PAGE_COUNT	16
389
390#ifdef CONFIG_PPC_BOOK3S_64
391#include <asm/book3s/64/mmu.h>
392#else /* CONFIG_PPC_BOOK3S_64 */
393
394#ifndef __ASSEMBLY__
395/* MMU initialization */
396extern void early_init_mmu(void);
397extern void early_init_mmu_secondary(void);
398extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
399				       phys_addr_t first_memblock_size);
400static inline void mmu_early_init_devtree(void) { }
401
402static inline void pkey_early_init_devtree(void) {}
403
404extern void *abatron_pteptrs[2];
405#endif /* __ASSEMBLY__ */
406#endif
407
408#if defined(CONFIG_PPC_BOOK3S_32)
409/* 32-bit classic hash table MMU */
410#include <asm/book3s/32/mmu-hash.h>
411#elif defined(CONFIG_PPC_MMU_NOHASH)
412#include <asm/nohash/mmu.h>
413#endif
414
415#if defined(CONFIG_FA_DUMP) || defined(CONFIG_PRESERVE_FA_DUMP)
416#define __HAVE_ARCH_RESERVED_KERNEL_PAGES
417#endif
418
419#endif /* __KERNEL__ */
420#endif /* _ASM_POWERPC_MMU_H_ */
421