1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Common registers for PPC AES implementation
4 *
5 * Copyright (c) 2015 Markus Stockhausen <stockhausen@collogia.de>
6 */
7
8#define rKS r0	/* copy of en-/decryption key pointer			*/
9#define rDP r3	/* destination pointer					*/
10#define rSP r4	/* source pointer					*/
11#define rKP r5	/* pointer to en-/decryption key pointer		*/
12#define rRR r6	/* en-/decryption rounds				*/
13#define rLN r7	/* length of data to be processed			*/
14#define rIP r8	/* potiner to IV (CBC/CTR/XTS modes)			*/
15#define rKT r9	/* pointer to tweak key (XTS mode)			*/
16#define rT0 r11	/* pointers to en-/decryption tables			*/
17#define rT1 r10
18#define rD0 r9	/* data 						*/
19#define rD1 r14
20#define rD2 r12
21#define rD3 r15
22#define rW0 r16	/* working registers					*/
23#define rW1 r17
24#define rW2 r18
25#define rW3 r19
26#define rW4 r20
27#define rW5 r21
28#define rW6 r22
29#define rW7 r23
30#define rI0 r24	/* IV							*/
31#define rI1 r25
32#define rI2 r26
33#define rI3 r27
34#define rG0 r28	/* endian reversed tweak (XTS mode)			*/
35#define rG1 r29
36#define rG2 r30
37#define rG3 r31
38