162306a36Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0-only
262306a36Sopenharmony_cimenu "Platform options"
362306a36Sopenharmony_ci
462306a36Sopenharmony_cicomment "Memory settings"
562306a36Sopenharmony_ci
662306a36Sopenharmony_ciconfig NIOS2_MEM_BASE
762306a36Sopenharmony_ci	hex "Memory base address"
862306a36Sopenharmony_ci	default "0x00000000"
962306a36Sopenharmony_ci	help
1062306a36Sopenharmony_ci	  This is the physical address of the memory that the kernel will run
1162306a36Sopenharmony_ci	  from. This address is used to link the kernel and setup initial memory
1262306a36Sopenharmony_ci	  management. You should take the raw memory address without any MMU
1362306a36Sopenharmony_ci	  or cache bits set.
1462306a36Sopenharmony_ci	  Please not that this address is used directly so you have to manually
1562306a36Sopenharmony_ci	  do address translation if it's connected to a bridge.
1662306a36Sopenharmony_ci
1762306a36Sopenharmony_cicomment "Device tree"
1862306a36Sopenharmony_ci
1962306a36Sopenharmony_ciconfig NIOS2_DTB_AT_PHYS_ADDR
2062306a36Sopenharmony_ci	bool "DTB at physical address"
2162306a36Sopenharmony_ci	help
2262306a36Sopenharmony_ci	  When enabled you can select a physical address to load the dtb from.
2362306a36Sopenharmony_ci	  Normally this address is passed by a bootloader such as u-boot but
2462306a36Sopenharmony_ci	  using this you can use a devicetree without a bootloader.
2562306a36Sopenharmony_ci	  This way you can store a devicetree in NOR flash or an onchip rom.
2662306a36Sopenharmony_ci	  Please note that this address is used directly so you have to manually
2762306a36Sopenharmony_ci	  do address translation if it's connected to a bridge. Also take into
2862306a36Sopenharmony_ci	  account that when using an MMU you'd have to ad 0xC0000000 to your
2962306a36Sopenharmony_ci	  address
3062306a36Sopenharmony_ci
3162306a36Sopenharmony_ciconfig NIOS2_DTB_PHYS_ADDR
3262306a36Sopenharmony_ci	hex "DTB Address"
3362306a36Sopenharmony_ci	depends on NIOS2_DTB_AT_PHYS_ADDR
3462306a36Sopenharmony_ci	default "0xC0000000"
3562306a36Sopenharmony_ci	help
3662306a36Sopenharmony_ci	  Physical address of a dtb blob.
3762306a36Sopenharmony_ci
3862306a36Sopenharmony_ciconfig NIOS2_DTB_SOURCE_BOOL
3962306a36Sopenharmony_ci	bool "Compile and link device tree into kernel image"
4062306a36Sopenharmony_ci	depends on !COMPILE_TEST
4162306a36Sopenharmony_ci	help
4262306a36Sopenharmony_ci	  This allows you to specify a dts (device tree source) file
4362306a36Sopenharmony_ci	  which will be compiled and linked into the kernel image.
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_ciconfig NIOS2_DTB_SOURCE
4662306a36Sopenharmony_ci	string "Device tree source file"
4762306a36Sopenharmony_ci	depends on NIOS2_DTB_SOURCE_BOOL
4862306a36Sopenharmony_ci	default ""
4962306a36Sopenharmony_ci	help
5062306a36Sopenharmony_ci	  Absolute path to the device tree source (dts) file describing your
5162306a36Sopenharmony_ci	  system.
5262306a36Sopenharmony_ci
5362306a36Sopenharmony_cicomment "Nios II instructions"
5462306a36Sopenharmony_ci
5562306a36Sopenharmony_ciconfig NIOS2_ARCH_REVISION
5662306a36Sopenharmony_ci	int "Select Nios II architecture revision"
5762306a36Sopenharmony_ci	range 1 2
5862306a36Sopenharmony_ci	default 1
5962306a36Sopenharmony_ci	help
6062306a36Sopenharmony_ci	  Select between Nios II R1 and Nios II R2 . The architectures
6162306a36Sopenharmony_ci	  are binary incompatible. Default is R1 .
6262306a36Sopenharmony_ci
6362306a36Sopenharmony_ciconfig NIOS2_HW_MUL_SUPPORT
6462306a36Sopenharmony_ci	bool "Enable MUL instruction"
6562306a36Sopenharmony_ci	help
6662306a36Sopenharmony_ci	  Set to true if you configured the Nios II to include the MUL
6762306a36Sopenharmony_ci	  instruction.  This will enable the -mhw-mul compiler flag.
6862306a36Sopenharmony_ci
6962306a36Sopenharmony_ciconfig NIOS2_HW_MULX_SUPPORT
7062306a36Sopenharmony_ci	bool "Enable MULX instruction"
7162306a36Sopenharmony_ci	help
7262306a36Sopenharmony_ci	  Set to true if you configured the Nios II to include the MULX
7362306a36Sopenharmony_ci	  instruction.  Enables the -mhw-mulx compiler flag.
7462306a36Sopenharmony_ci
7562306a36Sopenharmony_ciconfig NIOS2_HW_DIV_SUPPORT
7662306a36Sopenharmony_ci	bool "Enable DIV instruction"
7762306a36Sopenharmony_ci	help
7862306a36Sopenharmony_ci	  Set to true if you configured the Nios II to include the DIV
7962306a36Sopenharmony_ci	  instruction.  Enables the -mhw-div compiler flag.
8062306a36Sopenharmony_ci
8162306a36Sopenharmony_ciconfig NIOS2_BMX_SUPPORT
8262306a36Sopenharmony_ci	bool "Enable BMX instructions"
8362306a36Sopenharmony_ci	depends on NIOS2_ARCH_REVISION = 2
8462306a36Sopenharmony_ci	help
8562306a36Sopenharmony_ci	  Set to true if you configured the Nios II R2 to include
8662306a36Sopenharmony_ci	  the BMX Bit Manipulation Extension instructions. Enables
8762306a36Sopenharmony_ci	  the -mbmx compiler flag.
8862306a36Sopenharmony_ci
8962306a36Sopenharmony_ciconfig NIOS2_CDX_SUPPORT
9062306a36Sopenharmony_ci	bool "Enable CDX instructions"
9162306a36Sopenharmony_ci	depends on NIOS2_ARCH_REVISION = 2
9262306a36Sopenharmony_ci	help
9362306a36Sopenharmony_ci	  Set to true if you configured the Nios II R2 to include
9462306a36Sopenharmony_ci	  the CDX Bit Manipulation Extension instructions. Enables
9562306a36Sopenharmony_ci	  the -mcdx compiler flag.
9662306a36Sopenharmony_ci
9762306a36Sopenharmony_ciconfig NIOS2_FPU_SUPPORT
9862306a36Sopenharmony_ci	bool "Custom floating point instr support"
9962306a36Sopenharmony_ci	help
10062306a36Sopenharmony_ci	  Enables the -mcustom-fpu-cfg=60-1 compiler flag.
10162306a36Sopenharmony_ci
10262306a36Sopenharmony_ciconfig NIOS2_CI_SWAB_SUPPORT
10362306a36Sopenharmony_ci	bool "Byteswap custom instruction"
10462306a36Sopenharmony_ci	help
10562306a36Sopenharmony_ci	  Use the byteswap (endian converter) Nios II custom instruction provided
10662306a36Sopenharmony_ci	  by Altera and which can be enabled in QSYS builder. This accelerates
10762306a36Sopenharmony_ci	  endian conversions in the kernel (e.g. ntohs).
10862306a36Sopenharmony_ci
10962306a36Sopenharmony_ciconfig NIOS2_CI_SWAB_NO
11062306a36Sopenharmony_ci	int "Byteswap custom instruction number" if NIOS2_CI_SWAB_SUPPORT
11162306a36Sopenharmony_ci	default 0
11262306a36Sopenharmony_ci	help
11362306a36Sopenharmony_ci	  Number of the instruction as configured in QSYS Builder.
11462306a36Sopenharmony_ci
11562306a36Sopenharmony_cicomment "Cache settings"
11662306a36Sopenharmony_ci
11762306a36Sopenharmony_ciconfig CUSTOM_CACHE_SETTINGS
11862306a36Sopenharmony_ci	bool "Custom cache settings"
11962306a36Sopenharmony_ci	help
12062306a36Sopenharmony_ci	  This option allows you to tweak the cache settings used during early
12162306a36Sopenharmony_ci	  boot (where the information from device tree is not yet available).
12262306a36Sopenharmony_ci	  There should be no reason to change these values. Linux will work
12362306a36Sopenharmony_ci	  perfectly fine, even if the Nios II is configured with smaller caches.
12462306a36Sopenharmony_ci
12562306a36Sopenharmony_ci	  Say N here unless you know what you are doing.
12662306a36Sopenharmony_ci
12762306a36Sopenharmony_ciconfig NIOS2_DCACHE_SIZE
12862306a36Sopenharmony_ci	hex "D-Cache size" if CUSTOM_CACHE_SETTINGS
12962306a36Sopenharmony_ci	range 0x200 0x10000
13062306a36Sopenharmony_ci	default "0x800"
13162306a36Sopenharmony_ci	help
13262306a36Sopenharmony_ci	  Maximum possible data cache size.
13362306a36Sopenharmony_ci
13462306a36Sopenharmony_ciconfig NIOS2_DCACHE_LINE_SIZE
13562306a36Sopenharmony_ci	hex "D-Cache line size" if CUSTOM_CACHE_SETTINGS
13662306a36Sopenharmony_ci	range 0x10 0x20
13762306a36Sopenharmony_ci	default "0x20"
13862306a36Sopenharmony_ci	help
13962306a36Sopenharmony_ci	  Minimum possible data cache line size.
14062306a36Sopenharmony_ci
14162306a36Sopenharmony_ciconfig NIOS2_ICACHE_SIZE
14262306a36Sopenharmony_ci	hex "I-Cache size" if CUSTOM_CACHE_SETTINGS
14362306a36Sopenharmony_ci	range 0x200 0x10000
14462306a36Sopenharmony_ci	default "0x1000"
14562306a36Sopenharmony_ci	help
14662306a36Sopenharmony_ci	  Maximum possible instruction cache size.
14762306a36Sopenharmony_ci
14862306a36Sopenharmony_ciendmenu
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