162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright 2002 Integrated Device Technology, Inc. 462306a36Sopenharmony_ci * All rights reserved. 562306a36Sopenharmony_ci * 662306a36Sopenharmony_ci * GPIO register definition. 762306a36Sopenharmony_ci * 862306a36Sopenharmony_ci * Author : ryan.holmQVist@idt.com 962306a36Sopenharmony_ci * Date : 20011005 1062306a36Sopenharmony_ci * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com> 1162306a36Sopenharmony_ci * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org> 1262306a36Sopenharmony_ci */ 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci#ifndef _RC32434_GPIO_H_ 1562306a36Sopenharmony_ci#define _RC32434_GPIO_H_ 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_cistruct rb532_gpio_reg { 1862306a36Sopenharmony_ci u32 gpiofunc; /* GPIO Function Register 1962306a36Sopenharmony_ci * gpiofunc[x]==0 bit = gpio 2062306a36Sopenharmony_ci * func[x]==1 bit = altfunc 2162306a36Sopenharmony_ci */ 2262306a36Sopenharmony_ci u32 gpiocfg; /* GPIO Configuration Register 2362306a36Sopenharmony_ci * gpiocfg[x]==0 bit = input 2462306a36Sopenharmony_ci * gpiocfg[x]==1 bit = output 2562306a36Sopenharmony_ci */ 2662306a36Sopenharmony_ci u32 gpiod; /* GPIO Data Register 2762306a36Sopenharmony_ci * gpiod[x] read/write gpio pinX status 2862306a36Sopenharmony_ci */ 2962306a36Sopenharmony_ci u32 gpioilevel; /* GPIO Interrupt Status Register 3062306a36Sopenharmony_ci * interrupt level (see gpioistat) 3162306a36Sopenharmony_ci */ 3262306a36Sopenharmony_ci u32 gpioistat; /* Gpio Interrupt Status Register 3362306a36Sopenharmony_ci * istat[x] = (gpiod[x] == level[x]) 3462306a36Sopenharmony_ci * cleared in ISR (STICKY bits) 3562306a36Sopenharmony_ci */ 3662306a36Sopenharmony_ci u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */ 3762306a36Sopenharmony_ci}; 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_ci/* UART GPIO signals */ 4062306a36Sopenharmony_ci#define RC32434_UART0_SOUT (1 << 0) 4162306a36Sopenharmony_ci#define RC32434_UART0_SIN (1 << 1) 4262306a36Sopenharmony_ci#define RC32434_UART0_RTS (1 << 2) 4362306a36Sopenharmony_ci#define RC32434_UART0_CTS (1 << 3) 4462306a36Sopenharmony_ci 4562306a36Sopenharmony_ci/* M & P bus GPIO signals */ 4662306a36Sopenharmony_ci#define RC32434_MP_BIT_22 (1 << 4) 4762306a36Sopenharmony_ci#define RC32434_MP_BIT_23 (1 << 5) 4862306a36Sopenharmony_ci#define RC32434_MP_BIT_24 (1 << 6) 4962306a36Sopenharmony_ci#define RC32434_MP_BIT_25 (1 << 7) 5062306a36Sopenharmony_ci 5162306a36Sopenharmony_ci/* CPU GPIO signals */ 5262306a36Sopenharmony_ci#define RC32434_CPU_GPIO (1 << 8) 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ci/* Reserved GPIO signals */ 5562306a36Sopenharmony_ci#define RC32434_AF_SPARE_6 (1 << 9) 5662306a36Sopenharmony_ci#define RC32434_AF_SPARE_4 (1 << 10) 5762306a36Sopenharmony_ci#define RC32434_AF_SPARE_3 (1 << 11) 5862306a36Sopenharmony_ci#define RC32434_AF_SPARE_2 (1 << 12) 5962306a36Sopenharmony_ci 6062306a36Sopenharmony_ci/* PCI messaging unit */ 6162306a36Sopenharmony_ci#define RC32434_PCI_MSU_GPIO (1 << 13) 6262306a36Sopenharmony_ci 6362306a36Sopenharmony_ci/* NAND GPIO signals */ 6462306a36Sopenharmony_ci#define GPIO_RDY 8 6562306a36Sopenharmony_ci#define GPIO_WPX 9 6662306a36Sopenharmony_ci#define GPIO_ALE 10 6762306a36Sopenharmony_ci#define GPIO_CLE 11 6862306a36Sopenharmony_ci 6962306a36Sopenharmony_ci/* Compact Flash GPIO pin */ 7062306a36Sopenharmony_ci#define CF_GPIO_NUM 13 7162306a36Sopenharmony_ci 7262306a36Sopenharmony_ci/* S1 button GPIO (shared with UART0_SIN) */ 7362306a36Sopenharmony_ci#define GPIO_BTN_S1 1 7462306a36Sopenharmony_ci 7562306a36Sopenharmony_ciextern void rb532_gpio_set_ilevel(int bit, unsigned gpio); 7662306a36Sopenharmony_ciextern void rb532_gpio_set_istat(int bit, unsigned gpio); 7762306a36Sopenharmony_ciextern void rb532_gpio_set_func(unsigned gpio); 7862306a36Sopenharmony_ci 7962306a36Sopenharmony_ci#endif /* _RC32434_GPIO_H_ */ 80