162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (C) 2005 Mips Technologies 462306a36Sopenharmony_ci * Author: Chris Dearman, chris@mips.com derived from fpu.h 562306a36Sopenharmony_ci */ 662306a36Sopenharmony_ci#ifndef _ASM_DSP_H 762306a36Sopenharmony_ci#define _ASM_DSP_H 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci#include <asm/cpu.h> 1062306a36Sopenharmony_ci#include <asm/cpu-features.h> 1162306a36Sopenharmony_ci#include <asm/hazards.h> 1262306a36Sopenharmony_ci#include <asm/mipsregs.h> 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci#define DSP_DEFAULT 0x00000000 1562306a36Sopenharmony_ci#define DSP_MASK 0x3f 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ci#define __enable_dsp_hazard() \ 1862306a36Sopenharmony_cido { \ 1962306a36Sopenharmony_ci asm("_ehb"); \ 2062306a36Sopenharmony_ci} while (0) 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_cistatic inline void __init_dsp(void) 2362306a36Sopenharmony_ci{ 2462306a36Sopenharmony_ci mthi1(0); 2562306a36Sopenharmony_ci mtlo1(0); 2662306a36Sopenharmony_ci mthi2(0); 2762306a36Sopenharmony_ci mtlo2(0); 2862306a36Sopenharmony_ci mthi3(0); 2962306a36Sopenharmony_ci mtlo3(0); 3062306a36Sopenharmony_ci wrdsp(DSP_DEFAULT, DSP_MASK); 3162306a36Sopenharmony_ci} 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_cistatic inline void init_dsp(void) 3462306a36Sopenharmony_ci{ 3562306a36Sopenharmony_ci if (cpu_has_dsp) 3662306a36Sopenharmony_ci __init_dsp(); 3762306a36Sopenharmony_ci} 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_ci#define __save_dsp(tsk) \ 4062306a36Sopenharmony_cido { \ 4162306a36Sopenharmony_ci tsk->thread.dsp.dspr[0] = mfhi1(); \ 4262306a36Sopenharmony_ci tsk->thread.dsp.dspr[1] = mflo1(); \ 4362306a36Sopenharmony_ci tsk->thread.dsp.dspr[2] = mfhi2(); \ 4462306a36Sopenharmony_ci tsk->thread.dsp.dspr[3] = mflo2(); \ 4562306a36Sopenharmony_ci tsk->thread.dsp.dspr[4] = mfhi3(); \ 4662306a36Sopenharmony_ci tsk->thread.dsp.dspr[5] = mflo3(); \ 4762306a36Sopenharmony_ci tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); \ 4862306a36Sopenharmony_ci} while (0) 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ci#define save_dsp(tsk) \ 5162306a36Sopenharmony_cido { \ 5262306a36Sopenharmony_ci if (cpu_has_dsp) \ 5362306a36Sopenharmony_ci __save_dsp(tsk); \ 5462306a36Sopenharmony_ci} while (0) 5562306a36Sopenharmony_ci 5662306a36Sopenharmony_ci#define __restore_dsp(tsk) \ 5762306a36Sopenharmony_cido { \ 5862306a36Sopenharmony_ci mthi1(tsk->thread.dsp.dspr[0]); \ 5962306a36Sopenharmony_ci mtlo1(tsk->thread.dsp.dspr[1]); \ 6062306a36Sopenharmony_ci mthi2(tsk->thread.dsp.dspr[2]); \ 6162306a36Sopenharmony_ci mtlo2(tsk->thread.dsp.dspr[3]); \ 6262306a36Sopenharmony_ci mthi3(tsk->thread.dsp.dspr[4]); \ 6362306a36Sopenharmony_ci mtlo3(tsk->thread.dsp.dspr[5]); \ 6462306a36Sopenharmony_ci wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); \ 6562306a36Sopenharmony_ci} while (0) 6662306a36Sopenharmony_ci 6762306a36Sopenharmony_ci#define restore_dsp(tsk) \ 6862306a36Sopenharmony_cido { \ 6962306a36Sopenharmony_ci if (cpu_has_dsp) \ 7062306a36Sopenharmony_ci __restore_dsp(tsk); \ 7162306a36Sopenharmony_ci} while (0) 7262306a36Sopenharmony_ci 7362306a36Sopenharmony_ci#define __get_dsp_regs(tsk) \ 7462306a36Sopenharmony_ci({ \ 7562306a36Sopenharmony_ci if (tsk == current) \ 7662306a36Sopenharmony_ci __save_dsp(current); \ 7762306a36Sopenharmony_ci \ 7862306a36Sopenharmony_ci tsk->thread.dsp.dspr; \ 7962306a36Sopenharmony_ci}) 8062306a36Sopenharmony_ci 8162306a36Sopenharmony_ci#endif /* _ASM_DSP_H */ 82