162306a36Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0 262306a36Sopenharmony_ciif CPU_CAVIUM_OCTEON 362306a36Sopenharmony_ci 462306a36Sopenharmony_ciconfig CAVIUM_CN63XXP1 562306a36Sopenharmony_ci bool "Enable CN63XXP1 errata workarounds" 662306a36Sopenharmony_ci default "n" 762306a36Sopenharmony_ci help 862306a36Sopenharmony_ci The CN63XXP1 chip requires build time workarounds to 962306a36Sopenharmony_ci function reliably, select this option to enable them. These 1062306a36Sopenharmony_ci workarounds will cause a slight decrease in performance on 1162306a36Sopenharmony_ci non-CN63XXP1 hardware, so it is recommended to select "n" 1262306a36Sopenharmony_ci unless it is known the workarounds are needed. 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ciconfig CAVIUM_OCTEON_CVMSEG_SIZE 1562306a36Sopenharmony_ci int "Number of L1 cache lines reserved for CVMSEG memory" 1662306a36Sopenharmony_ci range 0 54 1762306a36Sopenharmony_ci default 0 if !CAVIUM_OCTEON_SOC 1862306a36Sopenharmony_ci default 1 if CAVIUM_OCTEON_SOC 1962306a36Sopenharmony_ci help 2062306a36Sopenharmony_ci CVMSEG LM is a segment that accesses portions of the dcache as a 2162306a36Sopenharmony_ci local memory; the larger CVMSEG is, the smaller the cache is. 2262306a36Sopenharmony_ci This selects the size of CVMSEG LM, which is in cache blocks. The 2362306a36Sopenharmony_ci legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is 2462306a36Sopenharmony_ci between zero and 6192 bytes). 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ciendif # CPU_CAVIUM_OCTEON 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ciif CAVIUM_OCTEON_SOC 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ciconfig CAVIUM_OCTEON_LOCK_L2 3162306a36Sopenharmony_ci bool "Lock often used kernel code in the L2" 3262306a36Sopenharmony_ci default "y" 3362306a36Sopenharmony_ci help 3462306a36Sopenharmony_ci Enable locking parts of the kernel into the L2 cache. 3562306a36Sopenharmony_ci 3662306a36Sopenharmony_ciconfig CAVIUM_OCTEON_LOCK_L2_TLB 3762306a36Sopenharmony_ci bool "Lock the TLB handler in L2" 3862306a36Sopenharmony_ci depends on CAVIUM_OCTEON_LOCK_L2 3962306a36Sopenharmony_ci default "y" 4062306a36Sopenharmony_ci help 4162306a36Sopenharmony_ci Lock the low level TLB fast path into L2. 4262306a36Sopenharmony_ci 4362306a36Sopenharmony_ciconfig CAVIUM_OCTEON_LOCK_L2_EXCEPTION 4462306a36Sopenharmony_ci bool "Lock the exception handler in L2" 4562306a36Sopenharmony_ci depends on CAVIUM_OCTEON_LOCK_L2 4662306a36Sopenharmony_ci default "y" 4762306a36Sopenharmony_ci help 4862306a36Sopenharmony_ci Lock the low level exception handler into L2. 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ciconfig CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 5162306a36Sopenharmony_ci bool "Lock the interrupt handler in L2" 5262306a36Sopenharmony_ci depends on CAVIUM_OCTEON_LOCK_L2 5362306a36Sopenharmony_ci default "y" 5462306a36Sopenharmony_ci help 5562306a36Sopenharmony_ci Lock the low level interrupt handler into L2. 5662306a36Sopenharmony_ci 5762306a36Sopenharmony_ciconfig CAVIUM_OCTEON_LOCK_L2_INTERRUPT 5862306a36Sopenharmony_ci bool "Lock the 2nd level interrupt handler in L2" 5962306a36Sopenharmony_ci depends on CAVIUM_OCTEON_LOCK_L2 6062306a36Sopenharmony_ci default "y" 6162306a36Sopenharmony_ci help 6262306a36Sopenharmony_ci Lock the 2nd level interrupt handler in L2. 6362306a36Sopenharmony_ci 6462306a36Sopenharmony_ciconfig CAVIUM_OCTEON_LOCK_L2_MEMCPY 6562306a36Sopenharmony_ci bool "Lock memcpy() in L2" 6662306a36Sopenharmony_ci depends on CAVIUM_OCTEON_LOCK_L2 6762306a36Sopenharmony_ci default "y" 6862306a36Sopenharmony_ci help 6962306a36Sopenharmony_ci Lock the kernel's implementation of memcpy() into L2. 7062306a36Sopenharmony_ci 7162306a36Sopenharmony_ciconfig CAVIUM_RESERVE32 7262306a36Sopenharmony_ci int "Memory to reserve for user processes shared region (MB)" 7362306a36Sopenharmony_ci range 0 1536 7462306a36Sopenharmony_ci default "0" 7562306a36Sopenharmony_ci help 7662306a36Sopenharmony_ci Reserve a shared memory region for user processes to use for hardware 7762306a36Sopenharmony_ci memory buffers. This is required for 32bit applications to be able to 7862306a36Sopenharmony_ci send and receive packets directly. Applications access this memory by 7962306a36Sopenharmony_ci memory mapping /dev/mem for the addresses in /proc/octeon_info. For 8062306a36Sopenharmony_ci optimal performance with HugeTLBs, keep this size an even number of 8162306a36Sopenharmony_ci megabytes. 8262306a36Sopenharmony_ci 8362306a36Sopenharmony_ciconfig OCTEON_ILM 8462306a36Sopenharmony_ci tristate "Module to measure interrupt latency using Octeon CIU Timer" 8562306a36Sopenharmony_ci help 8662306a36Sopenharmony_ci This driver is a module to measure interrupt latency using the 8762306a36Sopenharmony_ci the CIU Timers on Octeon. 8862306a36Sopenharmony_ci 8962306a36Sopenharmony_ci To compile this driver as a module, choose M here. The module 9062306a36Sopenharmony_ci will be called octeon-ilm 9162306a36Sopenharmony_ci 9262306a36Sopenharmony_ciendif # CAVIUM_OCTEON_SOC 93