162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Q40 master Chip Control 462306a36Sopenharmony_ci * RTC stuff merged for compactness. 562306a36Sopenharmony_ci*/ 662306a36Sopenharmony_ci 762306a36Sopenharmony_ci#ifndef _Q40_MASTER_H 862306a36Sopenharmony_ci#define _Q40_MASTER_H 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci#include <asm/raw_io.h> 1162306a36Sopenharmony_ci#include <asm/kmap.h> 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci#define q40_master_addr 0xff000000 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ci#define IIRQ_REG 0x0 /* internal IRQ reg */ 1662306a36Sopenharmony_ci#define EIRQ_REG 0x4 /* external ... */ 1762306a36Sopenharmony_ci#define KEYCODE_REG 0x1c /* value of received scancode */ 1862306a36Sopenharmony_ci#define DISPLAY_CONTROL_REG 0x18 1962306a36Sopenharmony_ci#define FRAME_CLEAR_REG 0x24 2062306a36Sopenharmony_ci#define LED_REG 0x30 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci#define Q40_LED_ON() master_outb(1,LED_REG) 2362306a36Sopenharmony_ci#define Q40_LED_OFF() master_outb(0,LED_REG) 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci#define INTERRUPT_REG IIRQ_REG /* "native" ints */ 2662306a36Sopenharmony_ci#define KEY_IRQ_ENABLE_REG 0x08 /**/ 2762306a36Sopenharmony_ci#define KEYBOARD_UNLOCK_REG 0x20 /* clear kb int */ 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci#define SAMPLE_ENABLE_REG 0x14 /* generate SAMPLE ints */ 3062306a36Sopenharmony_ci#define SAMPLE_RATE_REG 0x2c 3162306a36Sopenharmony_ci#define SAMPLE_CLEAR_REG 0x28 3262306a36Sopenharmony_ci#define SAMPLE_LOW 0x00 3362306a36Sopenharmony_ci#define SAMPLE_HIGH 0x01 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci#define FRAME_RATE_REG 0x38 /* generate FRAME ints at 200 HZ rate */ 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci#if 0 3862306a36Sopenharmony_ci#define SER_ENABLE_REG 0x0c /* allow serial ints to be generated */ 3962306a36Sopenharmony_ci#endif 4062306a36Sopenharmony_ci#define EXT_ENABLE_REG 0x10 /* ... rest of the ISA ints ... */ 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_ci 4362306a36Sopenharmony_ci#define master_inb(_reg_) in_8((unsigned char *)q40_master_addr+_reg_) 4462306a36Sopenharmony_ci#define master_outb(_b_,_reg_) out_8((unsigned char *)q40_master_addr+_reg_,_b_) 4562306a36Sopenharmony_ci 4662306a36Sopenharmony_ci/* RTC defines */ 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_ci#define Q40_RTC_BASE (0xff021ffc) 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ci#define Q40_RTC_YEAR (*(volatile unsigned char *)(Q40_RTC_BASE+0)) 5162306a36Sopenharmony_ci#define Q40_RTC_MNTH (*(volatile unsigned char *)(Q40_RTC_BASE-4)) 5262306a36Sopenharmony_ci#define Q40_RTC_DATE (*(volatile unsigned char *)(Q40_RTC_BASE-8)) 5362306a36Sopenharmony_ci#define Q40_RTC_DOW (*(volatile unsigned char *)(Q40_RTC_BASE-12)) 5462306a36Sopenharmony_ci#define Q40_RTC_HOUR (*(volatile unsigned char *)(Q40_RTC_BASE-16)) 5562306a36Sopenharmony_ci#define Q40_RTC_MINS (*(volatile unsigned char *)(Q40_RTC_BASE-20)) 5662306a36Sopenharmony_ci#define Q40_RTC_SECS (*(volatile unsigned char *)(Q40_RTC_BASE-24)) 5762306a36Sopenharmony_ci#define Q40_RTC_CTRL (*(volatile unsigned char *)(Q40_RTC_BASE-28)) 5862306a36Sopenharmony_ci 5962306a36Sopenharmony_ci/* some control bits */ 6062306a36Sopenharmony_ci#define Q40_RTC_READ 64 /* prepare for reading */ 6162306a36Sopenharmony_ci#define Q40_RTC_WRITE 128 6262306a36Sopenharmony_ci 6362306a36Sopenharmony_ci/* define some Q40 specific ints */ 6462306a36Sopenharmony_ci#include <asm/q40ints.h> 6562306a36Sopenharmony_ci 6662306a36Sopenharmony_ci/* misc defs */ 6762306a36Sopenharmony_ci#define DAC_LEFT ((unsigned char *)0xff008000) 6862306a36Sopenharmony_ci#define DAC_RIGHT ((unsigned char *)0xff008004) 6962306a36Sopenharmony_ci 7062306a36Sopenharmony_ci#endif /* _Q40_MASTER_H */ 71