162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/****************************************************************************/ 362306a36Sopenharmony_ci 462306a36Sopenharmony_ci/* 562306a36Sopenharmony_ci * mcftimer.h -- ColdFire internal TIMER support defines. 662306a36Sopenharmony_ci * 762306a36Sopenharmony_ci * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com> 862306a36Sopenharmony_ci * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 962306a36Sopenharmony_ci */ 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci/****************************************************************************/ 1262306a36Sopenharmony_ci#ifndef mcftimer_h 1362306a36Sopenharmony_ci#define mcftimer_h 1462306a36Sopenharmony_ci/****************************************************************************/ 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci/* 1762306a36Sopenharmony_ci * Define the TIMER register set addresses. 1862306a36Sopenharmony_ci */ 1962306a36Sopenharmony_ci#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ 2062306a36Sopenharmony_ci#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */ 2162306a36Sopenharmony_ci#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */ 2262306a36Sopenharmony_ci#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */ 2362306a36Sopenharmony_ci#if defined(CONFIG_M53xx) || defined(CONFIG_M5441x) 2462306a36Sopenharmony_ci#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */ 2562306a36Sopenharmony_ci#else 2662306a36Sopenharmony_ci#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ 2762306a36Sopenharmony_ci#endif 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci/* 3062306a36Sopenharmony_ci * Bit definitions for the Timer Mode Register (TMR). 3162306a36Sopenharmony_ci * Register bit flags are common across ColdFires. 3262306a36Sopenharmony_ci */ 3362306a36Sopenharmony_ci#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ 3462306a36Sopenharmony_ci#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ 3562306a36Sopenharmony_ci#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ 3662306a36Sopenharmony_ci#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ 3762306a36Sopenharmony_ci#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ 3862306a36Sopenharmony_ci#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ 3962306a36Sopenharmony_ci#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ 4062306a36Sopenharmony_ci#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ 4162306a36Sopenharmony_ci#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ 4262306a36Sopenharmony_ci#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ 4362306a36Sopenharmony_ci#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ 4462306a36Sopenharmony_ci#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ 4562306a36Sopenharmony_ci#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ 4662306a36Sopenharmony_ci#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ 4762306a36Sopenharmony_ci#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ 4862306a36Sopenharmony_ci#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ 4962306a36Sopenharmony_ci#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ 5062306a36Sopenharmony_ci 5162306a36Sopenharmony_ci/* 5262306a36Sopenharmony_ci * Bit definitions for the Timer Event Registers (TER). 5362306a36Sopenharmony_ci */ 5462306a36Sopenharmony_ci#define MCFTIMER_TER_CAP 0x01 /* Capture event */ 5562306a36Sopenharmony_ci#define MCFTIMER_TER_REF 0x02 /* Reference event */ 5662306a36Sopenharmony_ci 5762306a36Sopenharmony_ci/****************************************************************************/ 5862306a36Sopenharmony_ci#endif /* mcftimer_h */ 59