162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/****************************************************************************/ 362306a36Sopenharmony_ci 462306a36Sopenharmony_ci/* 562306a36Sopenharmony_ci * mcfpit.h -- ColdFire internal PIT timer support defines. 662306a36Sopenharmony_ci * 762306a36Sopenharmony_ci * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com) 862306a36Sopenharmony_ci */ 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci/****************************************************************************/ 1162306a36Sopenharmony_ci#ifndef mcfpit_h 1262306a36Sopenharmony_ci#define mcfpit_h 1362306a36Sopenharmony_ci/****************************************************************************/ 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ci/* 1662306a36Sopenharmony_ci * Define the PIT timer register address offsets. 1762306a36Sopenharmony_ci */ 1862306a36Sopenharmony_ci#define MCFPIT_PCSR 0x0 /* PIT control register */ 1962306a36Sopenharmony_ci#define MCFPIT_PMR 0x2 /* PIT modulus register */ 2062306a36Sopenharmony_ci#define MCFPIT_PCNTR 0x4 /* PIT count register */ 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci/* 2362306a36Sopenharmony_ci * Bit definitions for the PIT Control and Status register. 2462306a36Sopenharmony_ci */ 2562306a36Sopenharmony_ci#define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */ 2662306a36Sopenharmony_ci#define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */ 2762306a36Sopenharmony_ci#define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */ 2862306a36Sopenharmony_ci#define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */ 2962306a36Sopenharmony_ci#define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */ 3062306a36Sopenharmony_ci#define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */ 3162306a36Sopenharmony_ci#define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */ 3262306a36Sopenharmony_ci#define MCFPIT_PCSR_CLK128 0x0700 /* System clock divisor */ 3362306a36Sopenharmony_ci#define MCFPIT_PCSR_CLK256 0x0800 /* System clock divisor */ 3462306a36Sopenharmony_ci#define MCFPIT_PCSR_CLK512 0x0900 /* System clock divisor */ 3562306a36Sopenharmony_ci#define MCFPIT_PCSR_CLK1024 0x0a00 /* System clock divisor */ 3662306a36Sopenharmony_ci#define MCFPIT_PCSR_CLK2048 0x0b00 /* System clock divisor */ 3762306a36Sopenharmony_ci#define MCFPIT_PCSR_CLK4096 0x0c00 /* System clock divisor */ 3862306a36Sopenharmony_ci#define MCFPIT_PCSR_CLK8192 0x0d00 /* System clock divisor */ 3962306a36Sopenharmony_ci#define MCFPIT_PCSR_CLK16384 0x0e00 /* System clock divisor */ 4062306a36Sopenharmony_ci#define MCFPIT_PCSR_CLK32768 0x0f00 /* System clock divisor */ 4162306a36Sopenharmony_ci#define MCFPIT_PCSR_DOZE 0x0040 /* Clock run in doze mode */ 4262306a36Sopenharmony_ci#define MCFPIT_PCSR_HALTED 0x0020 /* Clock run in halt mode */ 4362306a36Sopenharmony_ci#define MCFPIT_PCSR_OVW 0x0010 /* Overwrite PIT counter now */ 4462306a36Sopenharmony_ci#define MCFPIT_PCSR_PIE 0x0008 /* Enable PIT interrupt */ 4562306a36Sopenharmony_ci#define MCFPIT_PCSR_PIF 0x0004 /* PIT interrupt flag */ 4662306a36Sopenharmony_ci#define MCFPIT_PCSR_RLD 0x0002 /* Reload counter */ 4762306a36Sopenharmony_ci#define MCFPIT_PCSR_EN 0x0001 /* Enable PIT */ 4862306a36Sopenharmony_ci#define MCFPIT_PCSR_DISABLE 0x0000 /* Disable PIT */ 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ci/****************************************************************************/ 5162306a36Sopenharmony_ci#endif /* mcfpit_h */ 52