162306a36Sopenharmony_ci|
262306a36Sopenharmony_ci|	x_fline.sa 3.3 1/10/91
362306a36Sopenharmony_ci|
462306a36Sopenharmony_ci|	fpsp_fline --- FPSP handler for fline exception
562306a36Sopenharmony_ci|
662306a36Sopenharmony_ci|	First determine if the exception is one of the unimplemented
762306a36Sopenharmony_ci|	floating point instructions.  If so, let fpsp_unimp handle it.
862306a36Sopenharmony_ci|	Next, determine if the instruction is an fmovecr with a non-zero
962306a36Sopenharmony_ci|	<ea> field.  If so, handle here and return.  Otherwise, it
1062306a36Sopenharmony_ci|	must be a real F-line exception.
1162306a36Sopenharmony_ci|
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ci|		Copyright (C) Motorola, Inc. 1990
1462306a36Sopenharmony_ci|			All Rights Reserved
1562306a36Sopenharmony_ci|
1662306a36Sopenharmony_ci|       For details on the license for this file, please see the
1762306a36Sopenharmony_ci|       file, README, in this same directory.
1862306a36Sopenharmony_ci
1962306a36Sopenharmony_ciX_FLINE:	|idnt    2,1 | Motorola 040 Floating Point Software Package
2062306a36Sopenharmony_ci
2162306a36Sopenharmony_ci	|section	8
2262306a36Sopenharmony_ci
2362306a36Sopenharmony_ci#include "fpsp.h"
2462306a36Sopenharmony_ci
2562306a36Sopenharmony_ci	|xref	real_fline
2662306a36Sopenharmony_ci	|xref	fpsp_unimp
2762306a36Sopenharmony_ci	|xref	uni_2
2862306a36Sopenharmony_ci	|xref	mem_read
2962306a36Sopenharmony_ci	|xref	fpsp_fmt_error
3062306a36Sopenharmony_ci
3162306a36Sopenharmony_ci	.global	fpsp_fline
3262306a36Sopenharmony_cifpsp_fline:
3362306a36Sopenharmony_ci|
3462306a36Sopenharmony_ci|	check for unimplemented vector first.  Use EXC_VEC-4 because
3562306a36Sopenharmony_ci|	the equate is valid only after a 'link a6' has pushed one more
3662306a36Sopenharmony_ci|	long onto the stack.
3762306a36Sopenharmony_ci|
3862306a36Sopenharmony_ci	cmpw	#UNIMP_VEC,EXC_VEC-4(%a7)
3962306a36Sopenharmony_ci	beql	fpsp_unimp
4062306a36Sopenharmony_ci
4162306a36Sopenharmony_ci|
4262306a36Sopenharmony_ci|	fmovecr with non-zero <ea> handling here
4362306a36Sopenharmony_ci|
4462306a36Sopenharmony_ci	subl	#4,%a7		|4 accounts for 2-word difference
4562306a36Sopenharmony_ci|				;between six word frame (unimp) and
4662306a36Sopenharmony_ci|				;four word frame
4762306a36Sopenharmony_ci	link	%a6,#-LOCAL_SIZE
4862306a36Sopenharmony_ci	fsave	-(%a7)
4962306a36Sopenharmony_ci	moveml	%d0-%d1/%a0-%a1,USER_DA(%a6)
5062306a36Sopenharmony_ci	moveal	EXC_PC+4(%a6),%a0	|get address of fline instruction
5162306a36Sopenharmony_ci	leal	L_SCR1(%a6),%a1	|use L_SCR1 as scratch
5262306a36Sopenharmony_ci	movel	#4,%d0
5362306a36Sopenharmony_ci	addl	#4,%a6		|to offset the sub.l #4,a7 above so that
5462306a36Sopenharmony_ci|				;a6 can point correctly to the stack frame
5562306a36Sopenharmony_ci|				;before branching to mem_read
5662306a36Sopenharmony_ci	bsrl	mem_read
5762306a36Sopenharmony_ci	subl	#4,%a6
5862306a36Sopenharmony_ci	movel	L_SCR1(%a6),%d0	|d0 contains the fline and command word
5962306a36Sopenharmony_ci	bfextu	%d0{#4:#3},%d1	|extract coprocessor id
6062306a36Sopenharmony_ci	cmpib	#1,%d1		|check if cpid=1
6162306a36Sopenharmony_ci	bne	not_mvcr	|exit if not
6262306a36Sopenharmony_ci	bfextu	%d0{#16:#6},%d1
6362306a36Sopenharmony_ci	cmpib	#0x17,%d1		|check if it is an FMOVECR encoding
6462306a36Sopenharmony_ci	bne	not_mvcr
6562306a36Sopenharmony_ci|				;if an FMOVECR instruction, fix stack
6662306a36Sopenharmony_ci|				;and go to FPSP_UNIMP
6762306a36Sopenharmony_cifix_stack:
6862306a36Sopenharmony_ci	cmpib	#VER_40,(%a7)	|test for orig unimp frame
6962306a36Sopenharmony_ci	bnes	ck_rev
7062306a36Sopenharmony_ci	subl	#UNIMP_40_SIZE-4,%a7 |emulate an orig fsave
7162306a36Sopenharmony_ci	moveb	#VER_40,(%a7)
7262306a36Sopenharmony_ci	moveb	#UNIMP_40_SIZE-4,1(%a7)
7362306a36Sopenharmony_ci	clrw	2(%a7)
7462306a36Sopenharmony_ci	bras	fix_con
7562306a36Sopenharmony_cick_rev:
7662306a36Sopenharmony_ci	cmpib	#VER_41,(%a7)	|test for rev unimp frame
7762306a36Sopenharmony_ci	bnel	fpsp_fmt_error	|if not $40 or $41, exit with error
7862306a36Sopenharmony_ci	subl	#UNIMP_41_SIZE-4,%a7 |emulate a rev fsave
7962306a36Sopenharmony_ci	moveb	#VER_41,(%a7)
8062306a36Sopenharmony_ci	moveb	#UNIMP_41_SIZE-4,1(%a7)
8162306a36Sopenharmony_ci	clrw	2(%a7)
8262306a36Sopenharmony_cifix_con:
8362306a36Sopenharmony_ci	movew	EXC_SR+4(%a6),EXC_SR(%a6) |move stacked sr to new position
8462306a36Sopenharmony_ci	movel	EXC_PC+4(%a6),EXC_PC(%a6) |move stacked pc to new position
8562306a36Sopenharmony_ci	fmovel	EXC_PC(%a6),%FPIAR |point FPIAR to fline inst
8662306a36Sopenharmony_ci	movel	#4,%d1
8762306a36Sopenharmony_ci	addl	%d1,EXC_PC(%a6)	|increment stacked pc value to next inst
8862306a36Sopenharmony_ci	movew	#0x202c,EXC_VEC(%a6) |reformat vector to unimp
8962306a36Sopenharmony_ci	clrl	EXC_EA(%a6)	|clear the EXC_EA field
9062306a36Sopenharmony_ci	movew	%d0,CMDREG1B(%a6) |move the lower word into CMDREG1B
9162306a36Sopenharmony_ci	clrl	E_BYTE(%a6)
9262306a36Sopenharmony_ci	bsetb	#UFLAG,T_BYTE(%a6)
9362306a36Sopenharmony_ci	moveml	USER_DA(%a6),%d0-%d1/%a0-%a1 |restore data registers
9462306a36Sopenharmony_ci	bral	uni_2
9562306a36Sopenharmony_ci
9662306a36Sopenharmony_cinot_mvcr:
9762306a36Sopenharmony_ci	moveml	USER_DA(%a6),%d0-%d1/%a0-%a1 |restore data registers
9862306a36Sopenharmony_ci	frestore (%a7)+
9962306a36Sopenharmony_ci	unlk	%a6
10062306a36Sopenharmony_ci	addl	#4,%a7
10162306a36Sopenharmony_ci	bral	real_fline
10262306a36Sopenharmony_ci
10362306a36Sopenharmony_ci	|end
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