1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
4 */
5#ifndef __ASM_CPU_INFO_H
6#define __ASM_CPU_INFO_H
7
8#include <linux/cache.h>
9#include <linux/types.h>
10
11#include <asm/loongarch.h>
12
13/* cache_desc->flags */
14enum {
15	CACHE_PRESENT	= (1 << 0),
16	CACHE_PRIVATE	= (1 << 1),	/* core private cache */
17	CACHE_INCLUSIVE	= (1 << 2),	/* include the inner level caches */
18};
19
20/*
21 * Descriptor for a cache
22 */
23struct cache_desc {
24	unsigned char type;
25	unsigned char level;
26	unsigned short sets;	/* Number of lines per set */
27	unsigned char ways;	/* Number of ways */
28	unsigned char linesz;	/* Size of line in bytes */
29	unsigned char flags;	/* Flags describing cache properties */
30};
31
32#define CACHE_LEVEL_MAX		3
33#define CACHE_LEAVES_MAX	6
34
35struct cpuinfo_loongarch {
36	u64			asid_cache;
37	unsigned long		asid_mask;
38
39	/*
40	 * Capability and feature descriptor structure for LoongArch CPU
41	 */
42	unsigned long long	options;
43	unsigned int		processor_id;
44	unsigned int		fpu_vers;
45	unsigned int		fpu_csr0;
46	unsigned int		fpu_mask;
47	unsigned int		cputype;
48	int			isa_level;
49	int			tlbsize;
50	int			tlbsizemtlb;
51	int			tlbsizestlbsets;
52	int			tlbsizestlbways;
53	int			cache_leaves_present; /* number of cache_leaves[] elements */
54	struct cache_desc	cache_leaves[CACHE_LEAVES_MAX];
55	int			core;   /* physical core number in package */
56	int			package;/* physical package number */
57	int			global_id; /* physical global thread number */
58	int			vabits; /* Virtual Address size in bits */
59	int			pabits; /* Physical Address size in bits */
60	unsigned int		ksave_mask; /* Usable KSave mask. */
61	unsigned int		watch_dreg_count;   /* Number data breakpoints */
62	unsigned int		watch_ireg_count;   /* Number instruction breakpoints */
63	unsigned int		watch_reg_use_cnt; /* min(NUM_WATCH_REGS, watch_dreg_count + watch_ireg_count), Usable by ptrace */
64} __aligned(SMP_CACHE_BYTES);
65
66extern struct cpuinfo_loongarch cpu_data[];
67#define boot_cpu_data cpu_data[0]
68#define current_cpu_data cpu_data[smp_processor_id()]
69#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
70
71extern void cpu_probe(void);
72
73extern const char *__cpu_family[];
74extern const char *__cpu_full_name[];
75#define cpu_family_string()	__cpu_family[raw_smp_processor_id()]
76#define cpu_full_name_string()	__cpu_full_name[raw_smp_processor_id()]
77
78struct seq_file;
79struct notifier_block;
80
81extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
82extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
83
84#define proc_cpuinfo_notifier(fn, pri)					\
85({									\
86	static struct notifier_block fn##_nb = {			\
87		.notifier_call = fn,					\
88		.priority = pri						\
89	};								\
90									\
91	register_proc_cpuinfo_notifier(&fn##_nb);			\
92})
93
94struct proc_cpuinfo_notifier_args {
95	struct seq_file *m;
96	unsigned long n;
97};
98
99static inline bool cpus_are_siblings(int cpua, int cpub)
100{
101	struct cpuinfo_loongarch *infoa = &cpu_data[cpua];
102	struct cpuinfo_loongarch *infob = &cpu_data[cpub];
103
104	if (infoa->package != infob->package)
105		return false;
106
107	if (infoa->core != infob->core)
108		return false;
109
110	return true;
111}
112
113static inline unsigned long cpu_asid_mask(struct cpuinfo_loongarch *cpuinfo)
114{
115	return cpuinfo->asid_mask;
116}
117
118static inline void set_cpu_asid_mask(struct cpuinfo_loongarch *cpuinfo,
119				     unsigned long asid_mask)
120{
121	cpuinfo->asid_mask = asid_mask;
122}
123
124#endif /* __ASM_CPU_INFO_H */
125