1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Cache operations for the cache instruction.
4 *
5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
6 */
7#ifndef __ASM_CACHEOPS_H
8#define __ASM_CACHEOPS_H
9
10/*
11 * Most cache ops are split into a 3 bit field identifying the cache, and a 2
12 * bit field identifying the cache operation.
13 */
14#define CacheOp_Cache			0x07
15#define CacheOp_Op			0x18
16
17#define Cache_LEAF0			0x00
18#define Cache_LEAF1			0x01
19#define Cache_LEAF2			0x02
20#define Cache_LEAF3			0x03
21#define Cache_LEAF4			0x04
22#define Cache_LEAF5			0x05
23
24#define Index_Invalidate		0x08
25#define Index_Writeback_Inv		0x08
26#define Hit_Invalidate			0x10
27#define Hit_Writeback_Inv		0x10
28#define CacheOp_User_Defined		0x18
29
30#define Index_Writeback_Inv_LEAF0	(Cache_LEAF0 | Index_Writeback_Inv)
31#define Index_Writeback_Inv_LEAF1	(Cache_LEAF1 | Index_Writeback_Inv)
32#define Index_Writeback_Inv_LEAF2	(Cache_LEAF2 | Index_Writeback_Inv)
33#define Index_Writeback_Inv_LEAF3	(Cache_LEAF3 | Index_Writeback_Inv)
34#define Index_Writeback_Inv_LEAF4	(Cache_LEAF4 | Index_Writeback_Inv)
35#define Index_Writeback_Inv_LEAF5	(Cache_LEAF5 | Index_Writeback_Inv)
36#define Hit_Writeback_Inv_LEAF0		(Cache_LEAF0 | Hit_Writeback_Inv)
37#define Hit_Writeback_Inv_LEAF1		(Cache_LEAF1 | Hit_Writeback_Inv)
38#define Hit_Writeback_Inv_LEAF2		(Cache_LEAF2 | Hit_Writeback_Inv)
39#define Hit_Writeback_Inv_LEAF3		(Cache_LEAF3 | Hit_Writeback_Inv)
40#define Hit_Writeback_Inv_LEAF4		(Cache_LEAF4 | Hit_Writeback_Inv)
41#define Hit_Writeback_Inv_LEAF5		(Cache_LEAF5 | Hit_Writeback_Inv)
42
43#endif	/* __ASM_CACHEOPS_H */
44