162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci 362306a36Sopenharmony_ci#ifndef __ASM_CSKY_BARRIER_H 462306a36Sopenharmony_ci#define __ASM_CSKY_BARRIER_H 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci#ifndef __ASSEMBLY__ 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci#define nop() asm volatile ("nop\n":::"memory") 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci#ifdef CONFIG_SMP 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci/* 1362306a36Sopenharmony_ci * bar.brwarws: ordering barrier for all load/store instructions 1462306a36Sopenharmony_ci * before/after 1562306a36Sopenharmony_ci * 1662306a36Sopenharmony_ci * |31|30 26|25 21|20 16|15 10|9 5|4 0| 1762306a36Sopenharmony_ci * 1 10000 00000 00000 100001 00001 0 bw br aw ar 1862306a36Sopenharmony_ci * 1962306a36Sopenharmony_ci * b: before 2062306a36Sopenharmony_ci * a: after 2162306a36Sopenharmony_ci * r: read 2262306a36Sopenharmony_ci * w: write 2362306a36Sopenharmony_ci * 2462306a36Sopenharmony_ci * Here are all combinations: 2562306a36Sopenharmony_ci * 2662306a36Sopenharmony_ci * bar.brw 2762306a36Sopenharmony_ci * bar.br 2862306a36Sopenharmony_ci * bar.bw 2962306a36Sopenharmony_ci * bar.arw 3062306a36Sopenharmony_ci * bar.ar 3162306a36Sopenharmony_ci * bar.aw 3262306a36Sopenharmony_ci * bar.brwarw 3362306a36Sopenharmony_ci * bar.brarw 3462306a36Sopenharmony_ci * bar.bwarw 3562306a36Sopenharmony_ci * bar.brwar 3662306a36Sopenharmony_ci * bar.brwaw 3762306a36Sopenharmony_ci * bar.brar 3862306a36Sopenharmony_ci * bar.bwaw 3962306a36Sopenharmony_ci */ 4062306a36Sopenharmony_ci#define FULL_FENCE ".long 0x842fc000\n" 4162306a36Sopenharmony_ci#define ACQUIRE_FENCE ".long 0x8427c000\n" 4262306a36Sopenharmony_ci#define RELEASE_FENCE ".long 0x842ec000\n" 4362306a36Sopenharmony_ci 4462306a36Sopenharmony_ci#define __bar_brw() asm volatile (".long 0x842cc000\n":::"memory") 4562306a36Sopenharmony_ci#define __bar_br() asm volatile (".long 0x8424c000\n":::"memory") 4662306a36Sopenharmony_ci#define __bar_bw() asm volatile (".long 0x8428c000\n":::"memory") 4762306a36Sopenharmony_ci#define __bar_arw() asm volatile (".long 0x8423c000\n":::"memory") 4862306a36Sopenharmony_ci#define __bar_ar() asm volatile (".long 0x8421c000\n":::"memory") 4962306a36Sopenharmony_ci#define __bar_aw() asm volatile (".long 0x8422c000\n":::"memory") 5062306a36Sopenharmony_ci#define __bar_brwarw() asm volatile (FULL_FENCE:::"memory") 5162306a36Sopenharmony_ci#define __bar_brarw() asm volatile (ACQUIRE_FENCE:::"memory") 5262306a36Sopenharmony_ci#define __bar_bwarw() asm volatile (".long 0x842bc000\n":::"memory") 5362306a36Sopenharmony_ci#define __bar_brwar() asm volatile (".long 0x842dc000\n":::"memory") 5462306a36Sopenharmony_ci#define __bar_brwaw() asm volatile (RELEASE_FENCE:::"memory") 5562306a36Sopenharmony_ci#define __bar_brar() asm volatile (".long 0x8425c000\n":::"memory") 5662306a36Sopenharmony_ci#define __bar_brar() asm volatile (".long 0x8425c000\n":::"memory") 5762306a36Sopenharmony_ci#define __bar_bwaw() asm volatile (".long 0x842ac000\n":::"memory") 5862306a36Sopenharmony_ci 5962306a36Sopenharmony_ci#define __smp_mb() __bar_brwarw() 6062306a36Sopenharmony_ci#define __smp_rmb() __bar_brar() 6162306a36Sopenharmony_ci#define __smp_wmb() __bar_bwaw() 6262306a36Sopenharmony_ci 6362306a36Sopenharmony_ci#define __smp_acquire_fence() __bar_brarw() 6462306a36Sopenharmony_ci#define __smp_release_fence() __bar_brwaw() 6562306a36Sopenharmony_ci 6662306a36Sopenharmony_ci#endif /* CONFIG_SMP */ 6762306a36Sopenharmony_ci 6862306a36Sopenharmony_ci/* 6962306a36Sopenharmony_ci * sync: completion barrier, all sync.xx instructions 7062306a36Sopenharmony_ci * guarantee the last response received by bus transaction 7162306a36Sopenharmony_ci * made by ld/st instructions before sync.s 7262306a36Sopenharmony_ci * sync.s: inherit from sync, but also shareable to other cores 7362306a36Sopenharmony_ci * sync.i: inherit from sync, but also flush cpu pipeline 7462306a36Sopenharmony_ci * sync.is: the same with sync.i + sync.s 7562306a36Sopenharmony_ci */ 7662306a36Sopenharmony_ci#define mb() asm volatile ("sync\n":::"memory") 7762306a36Sopenharmony_ci 7862306a36Sopenharmony_ci#ifdef CONFIG_CPU_HAS_CACHEV2 7962306a36Sopenharmony_ci/* 8062306a36Sopenharmony_ci * Using three sync.is to prevent speculative PTW 8162306a36Sopenharmony_ci */ 8262306a36Sopenharmony_ci#define sync_is() asm volatile ("sync.is\nsync.is\nsync.is\n":::"memory") 8362306a36Sopenharmony_ci#endif 8462306a36Sopenharmony_ci 8562306a36Sopenharmony_ci#include <asm-generic/barrier.h> 8662306a36Sopenharmony_ci 8762306a36Sopenharmony_ci#endif /* __ASSEMBLY__ */ 8862306a36Sopenharmony_ci#endif /* __ASM_CSKY_BARRIER_H */ 89