1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2012 ARM Ltd.
4 */
5#ifndef __ASM_PGTABLE_HWDEF_H
6#define __ASM_PGTABLE_HWDEF_H
7
8#include <asm/memory.h>
9
10/*
11 * Number of page-table levels required to address 'va_bits' wide
12 * address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT)
13 * bits with (PAGE_SHIFT - 3) bits at each page table level. Hence:
14 *
15 *  levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3))
16 *
17 * where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d))
18 *
19 * We cannot include linux/kernel.h which defines DIV_ROUND_UP here
20 * due to build issues. So we open code DIV_ROUND_UP here:
21 *
22 *	((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3))
23 *
24 * which gets simplified as :
25 */
26#define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3))
27
28/*
29 * Size mapped by an entry at level n ( 0 <= n <= 3)
30 * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits
31 * in the final page. The maximum number of translation levels supported by
32 * the architecture is 4. Hence, starting at level n, we have further
33 * ((4 - n) - 1) levels of translation excluding the offset within the page.
34 * So, the total number of bits mapped by an entry at level n is :
35 *
36 *  ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT
37 *
38 * Rearranging it a bit we get :
39 *   (4 - n) * (PAGE_SHIFT - 3) + 3
40 */
41#define ARM64_HW_PGTABLE_LEVEL_SHIFT(n)	((PAGE_SHIFT - 3) * (4 - (n)) + 3)
42
43#define PTRS_PER_PTE		(1 << (PAGE_SHIFT - 3))
44
45/*
46 * PMD_SHIFT determines the size a level 2 page table entry can map.
47 */
48#if CONFIG_PGTABLE_LEVELS > 2
49#define PMD_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(2)
50#define PMD_SIZE		(_AC(1, UL) << PMD_SHIFT)
51#define PMD_MASK		(~(PMD_SIZE-1))
52#define PTRS_PER_PMD		(1 << (PAGE_SHIFT - 3))
53#endif
54
55/*
56 * PUD_SHIFT determines the size a level 1 page table entry can map.
57 */
58#if CONFIG_PGTABLE_LEVELS > 3
59#define PUD_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(1)
60#define PUD_SIZE		(_AC(1, UL) << PUD_SHIFT)
61#define PUD_MASK		(~(PUD_SIZE-1))
62#define PTRS_PER_PUD		(1 << (PAGE_SHIFT - 3))
63#endif
64
65/*
66 * PGDIR_SHIFT determines the size a top-level page table entry can map
67 * (depending on the configuration, this level can be 0, 1 or 2).
68 */
69#define PGDIR_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS)
70#define PGDIR_SIZE		(_AC(1, UL) << PGDIR_SHIFT)
71#define PGDIR_MASK		(~(PGDIR_SIZE-1))
72#define PTRS_PER_PGD		(1 << (VA_BITS - PGDIR_SHIFT))
73
74/*
75 * Contiguous page definitions.
76 */
77#define CONT_PTE_SHIFT		(CONFIG_ARM64_CONT_PTE_SHIFT + PAGE_SHIFT)
78#define CONT_PTES		(1 << (CONT_PTE_SHIFT - PAGE_SHIFT))
79#define CONT_PTE_SIZE		(CONT_PTES * PAGE_SIZE)
80#define CONT_PTE_MASK		(~(CONT_PTE_SIZE - 1))
81
82#define CONT_PMD_SHIFT		(CONFIG_ARM64_CONT_PMD_SHIFT + PMD_SHIFT)
83#define CONT_PMDS		(1 << (CONT_PMD_SHIFT - PMD_SHIFT))
84#define CONT_PMD_SIZE		(CONT_PMDS * PMD_SIZE)
85#define CONT_PMD_MASK		(~(CONT_PMD_SIZE - 1))
86
87/*
88 * Hardware page table definitions.
89 *
90 * Level 0 descriptor (P4D).
91 */
92#define P4D_TYPE_TABLE		(_AT(p4dval_t, 3) << 0)
93#define P4D_TABLE_BIT		(_AT(p4dval_t, 1) << 1)
94#define P4D_TYPE_MASK		(_AT(p4dval_t, 3) << 0)
95#define P4D_TYPE_SECT		(_AT(p4dval_t, 1) << 0)
96#define P4D_SECT_RDONLY		(_AT(p4dval_t, 1) << 7)		/* AP[2] */
97#define P4D_TABLE_PXN		(_AT(p4dval_t, 1) << 59)
98#define P4D_TABLE_UXN		(_AT(p4dval_t, 1) << 60)
99
100/*
101 * Level 1 descriptor (PUD).
102 */
103#define PUD_TYPE_TABLE		(_AT(pudval_t, 3) << 0)
104#define PUD_TABLE_BIT		(_AT(pudval_t, 1) << 1)
105#define PUD_TYPE_MASK		(_AT(pudval_t, 3) << 0)
106#define PUD_TYPE_SECT		(_AT(pudval_t, 1) << 0)
107#define PUD_SECT_RDONLY		(_AT(pudval_t, 1) << 7)		/* AP[2] */
108#define PUD_TABLE_PXN		(_AT(pudval_t, 1) << 59)
109#define PUD_TABLE_UXN		(_AT(pudval_t, 1) << 60)
110
111/*
112 * Level 2 descriptor (PMD).
113 */
114#define PMD_TYPE_MASK		(_AT(pmdval_t, 3) << 0)
115#define PMD_TYPE_TABLE		(_AT(pmdval_t, 3) << 0)
116#define PMD_TYPE_SECT		(_AT(pmdval_t, 1) << 0)
117#define PMD_TABLE_BIT		(_AT(pmdval_t, 1) << 1)
118
119/*
120 * Section
121 */
122#define PMD_SECT_VALID		(_AT(pmdval_t, 1) << 0)
123#define PMD_SECT_USER		(_AT(pmdval_t, 1) << 6)		/* AP[1] */
124#define PMD_SECT_RDONLY		(_AT(pmdval_t, 1) << 7)		/* AP[2] */
125#define PMD_SECT_S		(_AT(pmdval_t, 3) << 8)
126#define PMD_SECT_AF		(_AT(pmdval_t, 1) << 10)
127#define PMD_SECT_NG		(_AT(pmdval_t, 1) << 11)
128#define PMD_SECT_CONT		(_AT(pmdval_t, 1) << 52)
129#define PMD_SECT_PXN		(_AT(pmdval_t, 1) << 53)
130#define PMD_SECT_UXN		(_AT(pmdval_t, 1) << 54)
131#define PMD_TABLE_PXN		(_AT(pmdval_t, 1) << 59)
132#define PMD_TABLE_UXN		(_AT(pmdval_t, 1) << 60)
133
134/*
135 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
136 */
137#define PMD_ATTRINDX(t)		(_AT(pmdval_t, (t)) << 2)
138#define PMD_ATTRINDX_MASK	(_AT(pmdval_t, 7) << 2)
139
140/*
141 * Level 3 descriptor (PTE).
142 */
143#define PTE_VALID		(_AT(pteval_t, 1) << 0)
144#define PTE_TYPE_MASK		(_AT(pteval_t, 3) << 0)
145#define PTE_TYPE_PAGE		(_AT(pteval_t, 3) << 0)
146#define PTE_TABLE_BIT		(_AT(pteval_t, 1) << 1)
147#define PTE_USER		(_AT(pteval_t, 1) << 6)		/* AP[1] */
148#define PTE_RDONLY		(_AT(pteval_t, 1) << 7)		/* AP[2] */
149#define PTE_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
150#define PTE_AF			(_AT(pteval_t, 1) << 10)	/* Access Flag */
151#define PTE_NG			(_AT(pteval_t, 1) << 11)	/* nG */
152#define PTE_GP			(_AT(pteval_t, 1) << 50)	/* BTI guarded */
153#define PTE_DBM			(_AT(pteval_t, 1) << 51)	/* Dirty Bit Management */
154#define PTE_CONT		(_AT(pteval_t, 1) << 52)	/* Contiguous range */
155#define PTE_PXN			(_AT(pteval_t, 1) << 53)	/* Privileged XN */
156#define PTE_UXN			(_AT(pteval_t, 1) << 54)	/* User XN */
157
158#define PTE_ADDR_LOW		(((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
159#ifdef CONFIG_ARM64_PA_BITS_52
160#define PTE_ADDR_HIGH		(_AT(pteval_t, 0xf) << 12)
161#define PTE_ADDR_MASK		(PTE_ADDR_LOW | PTE_ADDR_HIGH)
162#define PTE_ADDR_HIGH_SHIFT	36
163#else
164#define PTE_ADDR_MASK		PTE_ADDR_LOW
165#endif
166
167/*
168 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
169 */
170#define PTE_ATTRINDX(t)		(_AT(pteval_t, (t)) << 2)
171#define PTE_ATTRINDX_MASK	(_AT(pteval_t, 7) << 2)
172
173/*
174 * PIIndex[3:0] encoding (Permission Indirection Extension)
175 */
176#define PTE_PI_IDX_0	6	/* AP[1], USER */
177#define PTE_PI_IDX_1	51	/* DBM */
178#define PTE_PI_IDX_2	53	/* PXN */
179#define PTE_PI_IDX_3	54	/* UXN */
180
181/*
182 * Memory Attribute override for Stage-2 (MemAttr[3:0])
183 */
184#define PTE_S2_MEMATTR(t)	(_AT(pteval_t, (t)) << 2)
185
186/*
187 * Highest possible physical address supported.
188 */
189#define PHYS_MASK_SHIFT		(CONFIG_ARM64_PA_BITS)
190#define PHYS_MASK		((UL(1) << PHYS_MASK_SHIFT) - 1)
191
192#define TTBR_CNP_BIT		(UL(1) << 0)
193
194/*
195 * TCR flags.
196 */
197#define TCR_T0SZ_OFFSET		0
198#define TCR_T1SZ_OFFSET		16
199#define TCR_T0SZ(x)		((UL(64) - (x)) << TCR_T0SZ_OFFSET)
200#define TCR_T1SZ(x)		((UL(64) - (x)) << TCR_T1SZ_OFFSET)
201#define TCR_TxSZ(x)		(TCR_T0SZ(x) | TCR_T1SZ(x))
202#define TCR_TxSZ_WIDTH		6
203#define TCR_T0SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
204#define TCR_T1SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
205
206#define TCR_EPD0_SHIFT		7
207#define TCR_EPD0_MASK		(UL(1) << TCR_EPD0_SHIFT)
208#define TCR_IRGN0_SHIFT		8
209#define TCR_IRGN0_MASK		(UL(3) << TCR_IRGN0_SHIFT)
210#define TCR_IRGN0_NC		(UL(0) << TCR_IRGN0_SHIFT)
211#define TCR_IRGN0_WBWA		(UL(1) << TCR_IRGN0_SHIFT)
212#define TCR_IRGN0_WT		(UL(2) << TCR_IRGN0_SHIFT)
213#define TCR_IRGN0_WBnWA		(UL(3) << TCR_IRGN0_SHIFT)
214
215#define TCR_EPD1_SHIFT		23
216#define TCR_EPD1_MASK		(UL(1) << TCR_EPD1_SHIFT)
217#define TCR_IRGN1_SHIFT		24
218#define TCR_IRGN1_MASK		(UL(3) << TCR_IRGN1_SHIFT)
219#define TCR_IRGN1_NC		(UL(0) << TCR_IRGN1_SHIFT)
220#define TCR_IRGN1_WBWA		(UL(1) << TCR_IRGN1_SHIFT)
221#define TCR_IRGN1_WT		(UL(2) << TCR_IRGN1_SHIFT)
222#define TCR_IRGN1_WBnWA		(UL(3) << TCR_IRGN1_SHIFT)
223
224#define TCR_IRGN_NC		(TCR_IRGN0_NC | TCR_IRGN1_NC)
225#define TCR_IRGN_WBWA		(TCR_IRGN0_WBWA | TCR_IRGN1_WBWA)
226#define TCR_IRGN_WT		(TCR_IRGN0_WT | TCR_IRGN1_WT)
227#define TCR_IRGN_WBnWA		(TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA)
228#define TCR_IRGN_MASK		(TCR_IRGN0_MASK | TCR_IRGN1_MASK)
229
230
231#define TCR_ORGN0_SHIFT		10
232#define TCR_ORGN0_MASK		(UL(3) << TCR_ORGN0_SHIFT)
233#define TCR_ORGN0_NC		(UL(0) << TCR_ORGN0_SHIFT)
234#define TCR_ORGN0_WBWA		(UL(1) << TCR_ORGN0_SHIFT)
235#define TCR_ORGN0_WT		(UL(2) << TCR_ORGN0_SHIFT)
236#define TCR_ORGN0_WBnWA		(UL(3) << TCR_ORGN0_SHIFT)
237
238#define TCR_ORGN1_SHIFT		26
239#define TCR_ORGN1_MASK		(UL(3) << TCR_ORGN1_SHIFT)
240#define TCR_ORGN1_NC		(UL(0) << TCR_ORGN1_SHIFT)
241#define TCR_ORGN1_WBWA		(UL(1) << TCR_ORGN1_SHIFT)
242#define TCR_ORGN1_WT		(UL(2) << TCR_ORGN1_SHIFT)
243#define TCR_ORGN1_WBnWA		(UL(3) << TCR_ORGN1_SHIFT)
244
245#define TCR_ORGN_NC		(TCR_ORGN0_NC | TCR_ORGN1_NC)
246#define TCR_ORGN_WBWA		(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)
247#define TCR_ORGN_WT		(TCR_ORGN0_WT | TCR_ORGN1_WT)
248#define TCR_ORGN_WBnWA		(TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA)
249#define TCR_ORGN_MASK		(TCR_ORGN0_MASK | TCR_ORGN1_MASK)
250
251#define TCR_SH0_SHIFT		12
252#define TCR_SH0_MASK		(UL(3) << TCR_SH0_SHIFT)
253#define TCR_SH0_INNER		(UL(3) << TCR_SH0_SHIFT)
254
255#define TCR_SH1_SHIFT		28
256#define TCR_SH1_MASK		(UL(3) << TCR_SH1_SHIFT)
257#define TCR_SH1_INNER		(UL(3) << TCR_SH1_SHIFT)
258#define TCR_SHARED		(TCR_SH0_INNER | TCR_SH1_INNER)
259
260#define TCR_TG0_SHIFT		14
261#define TCR_TG0_MASK		(UL(3) << TCR_TG0_SHIFT)
262#define TCR_TG0_4K		(UL(0) << TCR_TG0_SHIFT)
263#define TCR_TG0_64K		(UL(1) << TCR_TG0_SHIFT)
264#define TCR_TG0_16K		(UL(2) << TCR_TG0_SHIFT)
265
266#define TCR_TG1_SHIFT		30
267#define TCR_TG1_MASK		(UL(3) << TCR_TG1_SHIFT)
268#define TCR_TG1_16K		(UL(1) << TCR_TG1_SHIFT)
269#define TCR_TG1_4K		(UL(2) << TCR_TG1_SHIFT)
270#define TCR_TG1_64K		(UL(3) << TCR_TG1_SHIFT)
271
272#define TCR_IPS_SHIFT		32
273#define TCR_IPS_MASK		(UL(7) << TCR_IPS_SHIFT)
274#define TCR_A1			(UL(1) << 22)
275#define TCR_ASID16		(UL(1) << 36)
276#define TCR_TBI0		(UL(1) << 37)
277#define TCR_TBI1		(UL(1) << 38)
278#define TCR_HA			(UL(1) << 39)
279#define TCR_HD			(UL(1) << 40)
280#define TCR_TBID1		(UL(1) << 52)
281#define TCR_NFD0		(UL(1) << 53)
282#define TCR_NFD1		(UL(1) << 54)
283#define TCR_E0PD0		(UL(1) << 55)
284#define TCR_E0PD1		(UL(1) << 56)
285#define TCR_TCMA0		(UL(1) << 57)
286#define TCR_TCMA1		(UL(1) << 58)
287
288/*
289 * TTBR.
290 */
291#ifdef CONFIG_ARM64_PA_BITS_52
292/*
293 * TTBR_ELx[1] is RES0 in this configuration.
294 */
295#define TTBR_BADDR_MASK_52	GENMASK_ULL(47, 2)
296#endif
297
298#ifdef CONFIG_ARM64_VA_BITS_52
299/* Must be at least 64-byte aligned to prevent corruption of the TTBR */
300#define TTBR1_BADDR_4852_OFFSET	(((UL(1) << (52 - PGDIR_SHIFT)) - \
301				 (UL(1) << (48 - PGDIR_SHIFT))) * 8)
302#endif
303
304#endif
305