162306a36Sopenharmony_ci// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Device Tree Source for the RZ/G2LC SMARC EVK parts
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright (C) 2022 Renesas Electronics Corp.
662306a36Sopenharmony_ci */
762306a36Sopenharmony_ci
862306a36Sopenharmony_ci#include <dt-bindings/gpio/gpio.h>
962306a36Sopenharmony_ci#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
1062306a36Sopenharmony_ci
1162306a36Sopenharmony_ci#include "rzg2lc-smarc-pinfunction.dtsi"
1262306a36Sopenharmony_ci#include "rz-smarc-common.dtsi"
1362306a36Sopenharmony_ci
1462306a36Sopenharmony_ci/ {
1562306a36Sopenharmony_ci	aliases {
1662306a36Sopenharmony_ci		serial1 = &scif1;
1762306a36Sopenharmony_ci		i2c2 = &i2c2;
1862306a36Sopenharmony_ci	};
1962306a36Sopenharmony_ci
2062306a36Sopenharmony_ci	osc1: cec-clock {
2162306a36Sopenharmony_ci		compatible = "fixed-clock";
2262306a36Sopenharmony_ci		#clock-cells = <0>;
2362306a36Sopenharmony_ci		clock-frequency = <12000000>;
2462306a36Sopenharmony_ci	};
2562306a36Sopenharmony_ci
2662306a36Sopenharmony_ci	hdmi-out {
2762306a36Sopenharmony_ci		compatible = "hdmi-connector";
2862306a36Sopenharmony_ci		type = "d";
2962306a36Sopenharmony_ci
3062306a36Sopenharmony_ci		port {
3162306a36Sopenharmony_ci			hdmi_con_out: endpoint {
3262306a36Sopenharmony_ci				remote-endpoint = <&adv7535_out>;
3362306a36Sopenharmony_ci			};
3462306a36Sopenharmony_ci		};
3562306a36Sopenharmony_ci	};
3662306a36Sopenharmony_ci};
3762306a36Sopenharmony_ci
3862306a36Sopenharmony_ci#if (SW_SCIF_CAN || SW_RSPI_CAN)
3962306a36Sopenharmony_ci&canfd {
4062306a36Sopenharmony_ci	pinctrl-0 = <&can1_pins>;
4162306a36Sopenharmony_ci	/delete-node/ channel@0;
4262306a36Sopenharmony_ci};
4362306a36Sopenharmony_ci#else
4462306a36Sopenharmony_ci&canfd {
4562306a36Sopenharmony_ci	/delete-property/ pinctrl-0;
4662306a36Sopenharmony_ci	/delete-property/ pinctrl-names;
4762306a36Sopenharmony_ci	status = "disabled";
4862306a36Sopenharmony_ci};
4962306a36Sopenharmony_ci#endif
5062306a36Sopenharmony_ci
5162306a36Sopenharmony_ci&cpu_dai {
5262306a36Sopenharmony_ci	sound-dai = <&ssi0>;
5362306a36Sopenharmony_ci};
5462306a36Sopenharmony_ci
5562306a36Sopenharmony_ci&dsi {
5662306a36Sopenharmony_ci	status = "okay";
5762306a36Sopenharmony_ci
5862306a36Sopenharmony_ci	ports {
5962306a36Sopenharmony_ci		#address-cells = <1>;
6062306a36Sopenharmony_ci		#size-cells = <0>;
6162306a36Sopenharmony_ci
6262306a36Sopenharmony_ci		port@0 {
6362306a36Sopenharmony_ci			reg = <0>;
6462306a36Sopenharmony_ci			dsi0_in: endpoint {
6562306a36Sopenharmony_ci			};
6662306a36Sopenharmony_ci		};
6762306a36Sopenharmony_ci
6862306a36Sopenharmony_ci		port@1 {
6962306a36Sopenharmony_ci			reg = <1>;
7062306a36Sopenharmony_ci			dsi0_out: endpoint {
7162306a36Sopenharmony_ci				data-lanes = <1 2 3 4>;
7262306a36Sopenharmony_ci				remote-endpoint = <&adv7535_in>;
7362306a36Sopenharmony_ci			};
7462306a36Sopenharmony_ci		};
7562306a36Sopenharmony_ci	};
7662306a36Sopenharmony_ci};
7762306a36Sopenharmony_ci
7862306a36Sopenharmony_ci&i2c1 {
7962306a36Sopenharmony_ci	adv7535: hdmi@3d {
8062306a36Sopenharmony_ci		compatible = "adi,adv7535";
8162306a36Sopenharmony_ci		reg = <0x3d>;
8262306a36Sopenharmony_ci
8362306a36Sopenharmony_ci		interrupt-parent = <&pinctrl>;
8462306a36Sopenharmony_ci		interrupts = <RZG2L_GPIO(43, 1) IRQ_TYPE_EDGE_FALLING>;
8562306a36Sopenharmony_ci		clocks = <&osc1>;
8662306a36Sopenharmony_ci		clock-names = "cec";
8762306a36Sopenharmony_ci		avdd-supply = <&reg_1p8v>;
8862306a36Sopenharmony_ci		dvdd-supply = <&reg_1p8v>;
8962306a36Sopenharmony_ci		pvdd-supply = <&reg_1p8v>;
9062306a36Sopenharmony_ci		a2vdd-supply = <&reg_1p8v>;
9162306a36Sopenharmony_ci		v3p3-supply = <&reg_3p3v>;
9262306a36Sopenharmony_ci		v1p2-supply = <&reg_1p8v>;
9362306a36Sopenharmony_ci
9462306a36Sopenharmony_ci		adi,dsi-lanes = <4>;
9562306a36Sopenharmony_ci
9662306a36Sopenharmony_ci		ports {
9762306a36Sopenharmony_ci			#address-cells = <1>;
9862306a36Sopenharmony_ci			#size-cells = <0>;
9962306a36Sopenharmony_ci
10062306a36Sopenharmony_ci			port@0 {
10162306a36Sopenharmony_ci				reg = <0>;
10262306a36Sopenharmony_ci				adv7535_in: endpoint {
10362306a36Sopenharmony_ci					remote-endpoint = <&dsi0_out>;
10462306a36Sopenharmony_ci				};
10562306a36Sopenharmony_ci			};
10662306a36Sopenharmony_ci
10762306a36Sopenharmony_ci			port@1 {
10862306a36Sopenharmony_ci				reg = <1>;
10962306a36Sopenharmony_ci				adv7535_out: endpoint {
11062306a36Sopenharmony_ci					remote-endpoint = <&hdmi_con_out>;
11162306a36Sopenharmony_ci				};
11262306a36Sopenharmony_ci			};
11362306a36Sopenharmony_ci		};
11462306a36Sopenharmony_ci	};
11562306a36Sopenharmony_ci};
11662306a36Sopenharmony_ci
11762306a36Sopenharmony_ci&i2c2 {
11862306a36Sopenharmony_ci	pinctrl-0 = <&i2c2_pins>;
11962306a36Sopenharmony_ci	pinctrl-names = "default";
12062306a36Sopenharmony_ci	clock-frequency = <400000>;
12162306a36Sopenharmony_ci
12262306a36Sopenharmony_ci	status = "okay";
12362306a36Sopenharmony_ci
12462306a36Sopenharmony_ci	wm8978: codec@1a {
12562306a36Sopenharmony_ci		compatible = "wlf,wm8978";
12662306a36Sopenharmony_ci		#sound-dai-cells = <0>;
12762306a36Sopenharmony_ci		reg = <0x1a>;
12862306a36Sopenharmony_ci	};
12962306a36Sopenharmony_ci};
13062306a36Sopenharmony_ci
13162306a36Sopenharmony_ci#if PMOD_MTU3
13262306a36Sopenharmony_ci&mtu3 {
13362306a36Sopenharmony_ci	pinctrl-0 = <&mtu3_pins>;
13462306a36Sopenharmony_ci	pinctrl-names = "default";
13562306a36Sopenharmony_ci
13662306a36Sopenharmony_ci	status = "okay";
13762306a36Sopenharmony_ci};
13862306a36Sopenharmony_ci
13962306a36Sopenharmony_ci&spi1 {
14062306a36Sopenharmony_ci	status = "disabled";
14162306a36Sopenharmony_ci};
14262306a36Sopenharmony_ci#endif
14362306a36Sopenharmony_ci
14462306a36Sopenharmony_ci/*
14562306a36Sopenharmony_ci * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
14662306a36Sopenharmony_ci * SW1 should be at position 2->3 so that SER0_CTS# line is activated
14762306a36Sopenharmony_ci * SW2 should be at position 2->3 so that SER0_TX line is activated
14862306a36Sopenharmony_ci * SW3 should be at position 2->3 so that SER0_RX line is activated
14962306a36Sopenharmony_ci * SW4 should be at position 2->3 so that SER0_RTS# line is activated
15062306a36Sopenharmony_ci */
15162306a36Sopenharmony_ci#if (!SW_SCIF_CAN && PMOD1_SER0)
15262306a36Sopenharmony_ci&scif1 {
15362306a36Sopenharmony_ci	pinctrl-0 = <&scif1_pins>;
15462306a36Sopenharmony_ci	pinctrl-names = "default";
15562306a36Sopenharmony_ci
15662306a36Sopenharmony_ci	uart-has-rtscts;
15762306a36Sopenharmony_ci	status = "okay";
15862306a36Sopenharmony_ci};
15962306a36Sopenharmony_ci#endif
16062306a36Sopenharmony_ci
16162306a36Sopenharmony_ci&ssi0 {
16262306a36Sopenharmony_ci	pinctrl-0 = <&ssi0_pins>;
16362306a36Sopenharmony_ci	pinctrl-names = "default";
16462306a36Sopenharmony_ci
16562306a36Sopenharmony_ci	status = "okay";
16662306a36Sopenharmony_ci};
16762306a36Sopenharmony_ci
16862306a36Sopenharmony_ci#if (SW_RSPI_CAN)
16962306a36Sopenharmony_ci&spi1 {
17062306a36Sopenharmony_ci	/delete-property/ pinctrl-0;
17162306a36Sopenharmony_ci	/delete-property/ pinctrl-names;
17262306a36Sopenharmony_ci	status = "disabled";
17362306a36Sopenharmony_ci};
17462306a36Sopenharmony_ci#endif
17562306a36Sopenharmony_ci
17662306a36Sopenharmony_ci&vccq_sdhi1 {
17762306a36Sopenharmony_ci	gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
17862306a36Sopenharmony_ci};
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