162306a36Sopenharmony_ci// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Device Tree Source for the RZ/G2LC SMARC SOM common parts
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright (C) 2021 Renesas Electronics Corp.
662306a36Sopenharmony_ci */
762306a36Sopenharmony_ci
862306a36Sopenharmony_ci#include <dt-bindings/gpio/gpio.h>
962306a36Sopenharmony_ci#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
1062306a36Sopenharmony_ci#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_ci/ {
1362306a36Sopenharmony_ci	aliases {
1462306a36Sopenharmony_ci		ethernet0 = &eth0;
1562306a36Sopenharmony_ci	};
1662306a36Sopenharmony_ci
1762306a36Sopenharmony_ci	chosen {
1862306a36Sopenharmony_ci		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
1962306a36Sopenharmony_ci	};
2062306a36Sopenharmony_ci
2162306a36Sopenharmony_ci	memory@48000000 {
2262306a36Sopenharmony_ci		device_type = "memory";
2362306a36Sopenharmony_ci		/* first 128MB is reserved for secure area. */
2462306a36Sopenharmony_ci		reg = <0x0 0x48000000 0x0 0x38000000>;
2562306a36Sopenharmony_ci	};
2662306a36Sopenharmony_ci
2762306a36Sopenharmony_ci	reg_1p8v: regulator-1p8v {
2862306a36Sopenharmony_ci		compatible = "regulator-fixed";
2962306a36Sopenharmony_ci		regulator-name = "fixed-1.8V";
3062306a36Sopenharmony_ci		regulator-min-microvolt = <1800000>;
3162306a36Sopenharmony_ci		regulator-max-microvolt = <1800000>;
3262306a36Sopenharmony_ci		regulator-boot-on;
3362306a36Sopenharmony_ci		regulator-always-on;
3462306a36Sopenharmony_ci	};
3562306a36Sopenharmony_ci
3662306a36Sopenharmony_ci	reg_3p3v: regulator-3p3v {
3762306a36Sopenharmony_ci		compatible = "regulator-fixed";
3862306a36Sopenharmony_ci		regulator-name = "fixed-3.3V";
3962306a36Sopenharmony_ci		regulator-min-microvolt = <3300000>;
4062306a36Sopenharmony_ci		regulator-max-microvolt = <3300000>;
4162306a36Sopenharmony_ci		regulator-boot-on;
4262306a36Sopenharmony_ci		regulator-always-on;
4362306a36Sopenharmony_ci	};
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_ci	reg_1p1v: regulator-vdd-core {
4662306a36Sopenharmony_ci		compatible = "regulator-fixed";
4762306a36Sopenharmony_ci		regulator-name = "fixed-1.1V";
4862306a36Sopenharmony_ci		regulator-min-microvolt = <1100000>;
4962306a36Sopenharmony_ci		regulator-max-microvolt = <1100000>;
5062306a36Sopenharmony_ci		regulator-boot-on;
5162306a36Sopenharmony_ci		regulator-always-on;
5262306a36Sopenharmony_ci	};
5362306a36Sopenharmony_ci
5462306a36Sopenharmony_ci	vccq_sdhi0: regulator-vccq-sdhi0 {
5562306a36Sopenharmony_ci		compatible = "regulator-gpio";
5662306a36Sopenharmony_ci
5762306a36Sopenharmony_ci		regulator-name = "SDHI0 VccQ";
5862306a36Sopenharmony_ci		regulator-min-microvolt = <1800000>;
5962306a36Sopenharmony_ci		regulator-max-microvolt = <3300000>;
6062306a36Sopenharmony_ci		states = <3300000 1>, <1800000 0>;
6162306a36Sopenharmony_ci		regulator-boot-on;
6262306a36Sopenharmony_ci		gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
6362306a36Sopenharmony_ci		regulator-always-on;
6462306a36Sopenharmony_ci	};
6562306a36Sopenharmony_ci
6662306a36Sopenharmony_ci	/* 32.768kHz crystal */
6762306a36Sopenharmony_ci	x2: x2-clock {
6862306a36Sopenharmony_ci		compatible = "fixed-clock";
6962306a36Sopenharmony_ci		#clock-cells = <0>;
7062306a36Sopenharmony_ci		clock-frequency = <32768>;
7162306a36Sopenharmony_ci	};
7262306a36Sopenharmony_ci};
7362306a36Sopenharmony_ci
7462306a36Sopenharmony_ci&eth0 {
7562306a36Sopenharmony_ci	pinctrl-0 = <&eth0_pins>;
7662306a36Sopenharmony_ci	pinctrl-names = "default";
7762306a36Sopenharmony_ci	phy-handle = <&phy0>;
7862306a36Sopenharmony_ci	phy-mode = "rgmii-id";
7962306a36Sopenharmony_ci	status = "okay";
8062306a36Sopenharmony_ci
8162306a36Sopenharmony_ci	phy0: ethernet-phy@7 {
8262306a36Sopenharmony_ci		compatible = "ethernet-phy-id0022.1640",
8362306a36Sopenharmony_ci			     "ethernet-phy-ieee802.3-c22";
8462306a36Sopenharmony_ci		reg = <7>;
8562306a36Sopenharmony_ci		interrupt-parent = <&irqc>;
8662306a36Sopenharmony_ci		interrupts = <RZG2L_IRQ0 IRQ_TYPE_LEVEL_LOW>;
8762306a36Sopenharmony_ci		rxc-skew-psec = <2400>;
8862306a36Sopenharmony_ci		txc-skew-psec = <2400>;
8962306a36Sopenharmony_ci		rxdv-skew-psec = <0>;
9062306a36Sopenharmony_ci		txen-skew-psec = <0>;
9162306a36Sopenharmony_ci		rxd0-skew-psec = <0>;
9262306a36Sopenharmony_ci		rxd1-skew-psec = <0>;
9362306a36Sopenharmony_ci		rxd2-skew-psec = <0>;
9462306a36Sopenharmony_ci		rxd3-skew-psec = <0>;
9562306a36Sopenharmony_ci		txd0-skew-psec = <0>;
9662306a36Sopenharmony_ci		txd1-skew-psec = <0>;
9762306a36Sopenharmony_ci		txd2-skew-psec = <0>;
9862306a36Sopenharmony_ci		txd3-skew-psec = <0>;
9962306a36Sopenharmony_ci	};
10062306a36Sopenharmony_ci};
10162306a36Sopenharmony_ci
10262306a36Sopenharmony_ci&extal_clk {
10362306a36Sopenharmony_ci	clock-frequency = <24000000>;
10462306a36Sopenharmony_ci};
10562306a36Sopenharmony_ci
10662306a36Sopenharmony_ci&gpu {
10762306a36Sopenharmony_ci	mali-supply = <&reg_1p1v>;
10862306a36Sopenharmony_ci};
10962306a36Sopenharmony_ci
11062306a36Sopenharmony_ci&i2c2 {
11162306a36Sopenharmony_ci	raa215300: pmic@12 {
11262306a36Sopenharmony_ci		compatible = "renesas,raa215300";
11362306a36Sopenharmony_ci		reg = <0x12>, <0x6f>;
11462306a36Sopenharmony_ci		reg-names = "main", "rtc";
11562306a36Sopenharmony_ci
11662306a36Sopenharmony_ci		clocks = <&x2>;
11762306a36Sopenharmony_ci		clock-names = "xin";
11862306a36Sopenharmony_ci	};
11962306a36Sopenharmony_ci};
12062306a36Sopenharmony_ci
12162306a36Sopenharmony_ci&ostm1 {
12262306a36Sopenharmony_ci	status = "okay";
12362306a36Sopenharmony_ci};
12462306a36Sopenharmony_ci
12562306a36Sopenharmony_ci&ostm2 {
12662306a36Sopenharmony_ci	status = "okay";
12762306a36Sopenharmony_ci};
12862306a36Sopenharmony_ci
12962306a36Sopenharmony_ci&pinctrl {
13062306a36Sopenharmony_ci	eth0_pins: eth0 {
13162306a36Sopenharmony_ci		pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
13262306a36Sopenharmony_ci			 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
13362306a36Sopenharmony_ci			 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
13462306a36Sopenharmony_ci			 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
13562306a36Sopenharmony_ci			 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
13662306a36Sopenharmony_ci			 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
13762306a36Sopenharmony_ci			 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
13862306a36Sopenharmony_ci			 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
13962306a36Sopenharmony_ci			 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
14062306a36Sopenharmony_ci			 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
14162306a36Sopenharmony_ci			 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
14262306a36Sopenharmony_ci			 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
14362306a36Sopenharmony_ci			 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
14462306a36Sopenharmony_ci			 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
14562306a36Sopenharmony_ci			 <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
14662306a36Sopenharmony_ci			 <RZG2L_PORT_PINMUX(0, 0, 1)>;  /* IRQ0 */
14762306a36Sopenharmony_ci	};
14862306a36Sopenharmony_ci
14962306a36Sopenharmony_ci	gpio-sd0-pwr-en-hog {
15062306a36Sopenharmony_ci		gpio-hog;
15162306a36Sopenharmony_ci		gpios = <RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>;
15262306a36Sopenharmony_ci		output-high;
15362306a36Sopenharmony_ci		line-name = "gpio_sd0_pwr_en";
15462306a36Sopenharmony_ci	};
15562306a36Sopenharmony_ci
15662306a36Sopenharmony_ci	qspi0_pins: qspi0 {
15762306a36Sopenharmony_ci		qspi0-data {
15862306a36Sopenharmony_ci			pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
15962306a36Sopenharmony_ci			power-source = <1800>;
16062306a36Sopenharmony_ci		};
16162306a36Sopenharmony_ci
16262306a36Sopenharmony_ci		qspi0-ctrl {
16362306a36Sopenharmony_ci			pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
16462306a36Sopenharmony_ci			power-source = <1800>;
16562306a36Sopenharmony_ci		};
16662306a36Sopenharmony_ci	};
16762306a36Sopenharmony_ci
16862306a36Sopenharmony_ci	/*
16962306a36Sopenharmony_ci	 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
17062306a36Sopenharmony_ci	 * The below switch logic can be used to select the device between
17162306a36Sopenharmony_ci	 * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
17262306a36Sopenharmony_ci	 * SW1[2] should be at OFF position to enable 64 GB eMMC
17362306a36Sopenharmony_ci	 * SW1[2] should be at position ON to enable uSD card CN3
17462306a36Sopenharmony_ci	 */
17562306a36Sopenharmony_ci	gpio-sd0-dev-sel-hog {
17662306a36Sopenharmony_ci		gpio-hog;
17762306a36Sopenharmony_ci		gpios = <RZG2L_GPIO(40, 2) GPIO_ACTIVE_HIGH>;
17862306a36Sopenharmony_ci		output-high;
17962306a36Sopenharmony_ci		line-name = "gpio_sd0_dev_sel";
18062306a36Sopenharmony_ci	};
18162306a36Sopenharmony_ci
18262306a36Sopenharmony_ci	sdhi0_emmc_pins: sd0emmc {
18362306a36Sopenharmony_ci		sd0_emmc_data {
18462306a36Sopenharmony_ci			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
18562306a36Sopenharmony_ci			       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
18662306a36Sopenharmony_ci			power-source = <1800>;
18762306a36Sopenharmony_ci		};
18862306a36Sopenharmony_ci
18962306a36Sopenharmony_ci		sd0_emmc_ctrl {
19062306a36Sopenharmony_ci			pins = "SD0_CLK", "SD0_CMD";
19162306a36Sopenharmony_ci			power-source = <1800>;
19262306a36Sopenharmony_ci		};
19362306a36Sopenharmony_ci
19462306a36Sopenharmony_ci		sd0_emmc_rst {
19562306a36Sopenharmony_ci			pins = "SD0_RST#";
19662306a36Sopenharmony_ci			power-source = <1800>;
19762306a36Sopenharmony_ci		};
19862306a36Sopenharmony_ci	};
19962306a36Sopenharmony_ci
20062306a36Sopenharmony_ci	sdhi0_pins: sd0 {
20162306a36Sopenharmony_ci		sd0_data {
20262306a36Sopenharmony_ci			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
20362306a36Sopenharmony_ci			power-source = <3300>;
20462306a36Sopenharmony_ci		};
20562306a36Sopenharmony_ci
20662306a36Sopenharmony_ci		sd0_ctrl {
20762306a36Sopenharmony_ci			pins = "SD0_CLK", "SD0_CMD";
20862306a36Sopenharmony_ci			power-source = <3300>;
20962306a36Sopenharmony_ci		};
21062306a36Sopenharmony_ci
21162306a36Sopenharmony_ci		sd0_mux {
21262306a36Sopenharmony_ci			pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
21362306a36Sopenharmony_ci		};
21462306a36Sopenharmony_ci	};
21562306a36Sopenharmony_ci
21662306a36Sopenharmony_ci	sdhi0_pins_uhs: sd0_uhs {
21762306a36Sopenharmony_ci		sd0_data_uhs {
21862306a36Sopenharmony_ci			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
21962306a36Sopenharmony_ci			power-source = <1800>;
22062306a36Sopenharmony_ci		};
22162306a36Sopenharmony_ci
22262306a36Sopenharmony_ci		sd0_ctrl_uhs {
22362306a36Sopenharmony_ci			pins = "SD0_CLK", "SD0_CMD";
22462306a36Sopenharmony_ci			power-source = <1800>;
22562306a36Sopenharmony_ci		};
22662306a36Sopenharmony_ci
22762306a36Sopenharmony_ci		sd0_mux_uhs {
22862306a36Sopenharmony_ci			pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
22962306a36Sopenharmony_ci		};
23062306a36Sopenharmony_ci	};
23162306a36Sopenharmony_ci};
23262306a36Sopenharmony_ci
23362306a36Sopenharmony_ci&sbc {
23462306a36Sopenharmony_ci	pinctrl-0 = <&qspi0_pins>;
23562306a36Sopenharmony_ci	pinctrl-names = "default";
23662306a36Sopenharmony_ci	status = "okay";
23762306a36Sopenharmony_ci
23862306a36Sopenharmony_ci	flash@0 {
23962306a36Sopenharmony_ci		compatible = "micron,mt25qu512a", "jedec,spi-nor";
24062306a36Sopenharmony_ci		reg = <0>;
24162306a36Sopenharmony_ci		m25p,fast-read;
24262306a36Sopenharmony_ci		spi-max-frequency = <50000000>;
24362306a36Sopenharmony_ci		spi-rx-bus-width = <4>;
24462306a36Sopenharmony_ci
24562306a36Sopenharmony_ci		partitions {
24662306a36Sopenharmony_ci			compatible = "fixed-partitions";
24762306a36Sopenharmony_ci			#address-cells = <1>;
24862306a36Sopenharmony_ci			#size-cells = <1>;
24962306a36Sopenharmony_ci
25062306a36Sopenharmony_ci			boot@0 {
25162306a36Sopenharmony_ci				reg = <0x00000000 0x2000000>;
25262306a36Sopenharmony_ci				read-only;
25362306a36Sopenharmony_ci			};
25462306a36Sopenharmony_ci			user@2000000 {
25562306a36Sopenharmony_ci				reg = <0x2000000 0x2000000>;
25662306a36Sopenharmony_ci			};
25762306a36Sopenharmony_ci		};
25862306a36Sopenharmony_ci	};
25962306a36Sopenharmony_ci};
26062306a36Sopenharmony_ci
26162306a36Sopenharmony_ci#if (!SW_SD0_DEV_SEL)
26262306a36Sopenharmony_ci&sdhi0 {
26362306a36Sopenharmony_ci	pinctrl-0 = <&sdhi0_pins>;
26462306a36Sopenharmony_ci	pinctrl-1 = <&sdhi0_pins_uhs>;
26562306a36Sopenharmony_ci	pinctrl-names = "default", "state_uhs";
26662306a36Sopenharmony_ci
26762306a36Sopenharmony_ci	vmmc-supply = <&reg_3p3v>;
26862306a36Sopenharmony_ci	vqmmc-supply = <&vccq_sdhi0>;
26962306a36Sopenharmony_ci	bus-width = <4>;
27062306a36Sopenharmony_ci	sd-uhs-sdr50;
27162306a36Sopenharmony_ci	sd-uhs-sdr104;
27262306a36Sopenharmony_ci	status = "okay";
27362306a36Sopenharmony_ci};
27462306a36Sopenharmony_ci#endif
27562306a36Sopenharmony_ci
27662306a36Sopenharmony_ci#if SW_SD0_DEV_SEL
27762306a36Sopenharmony_ci&sdhi0 {
27862306a36Sopenharmony_ci	pinctrl-0 = <&sdhi0_emmc_pins>;
27962306a36Sopenharmony_ci	pinctrl-1 = <&sdhi0_emmc_pins>;
28062306a36Sopenharmony_ci	pinctrl-names = "default", "state_uhs";
28162306a36Sopenharmony_ci
28262306a36Sopenharmony_ci	vmmc-supply = <&reg_3p3v>;
28362306a36Sopenharmony_ci	vqmmc-supply = <&reg_1p8v>;
28462306a36Sopenharmony_ci	bus-width = <8>;
28562306a36Sopenharmony_ci	mmc-hs200-1_8v;
28662306a36Sopenharmony_ci	non-removable;
28762306a36Sopenharmony_ci	fixed-emmc-driver-type = <1>;
28862306a36Sopenharmony_ci	status = "okay";
28962306a36Sopenharmony_ci};
29062306a36Sopenharmony_ci#endif
29162306a36Sopenharmony_ci
29262306a36Sopenharmony_ci&wdt0 {
29362306a36Sopenharmony_ci	status = "okay";
29462306a36Sopenharmony_ci	timeout-sec = <60>;
29562306a36Sopenharmony_ci};
29662306a36Sopenharmony_ci
29762306a36Sopenharmony_ci&wdt1 {
29862306a36Sopenharmony_ci	status = "okay";
29962306a36Sopenharmony_ci	timeout-sec = <60>;
30062306a36Sopenharmony_ci};
301