162306a36Sopenharmony_ci// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Device Tree Source for the RZ/G2LC SMARC EVK board
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright (C) 2021 Renesas Electronics Corp.
662306a36Sopenharmony_ci */
762306a36Sopenharmony_ci
862306a36Sopenharmony_ci/dts-v1/;
962306a36Sopenharmony_ci
1062306a36Sopenharmony_ci/*
1162306a36Sopenharmony_ci * DIP-Switch SW1 setting on SoM
1262306a36Sopenharmony_ci * 1 : High; 0: Low
1362306a36Sopenharmony_ci * SW1-2 : SW_SD0_DEV_SEL	(1: eMMC; 0: uSD)
1462306a36Sopenharmony_ci * SW1-3 : SW_SCIF_CAN		(1: CAN1; 0: SCIF1)
1562306a36Sopenharmony_ci * SW1-4 : SW_RSPI_CAN		(1: CAN1; 0: RSPI1)
1662306a36Sopenharmony_ci * SW1-5 : SW_I2S0_I2S1		(1: I2S2 (HDMI audio); 0: I2S0)
1762306a36Sopenharmony_ci * Please change below macros according to SW1 setting
1862306a36Sopenharmony_ci */
1962306a36Sopenharmony_ci
2062306a36Sopenharmony_ci#define SW_SD0_DEV_SEL	1
2162306a36Sopenharmony_ci
2262306a36Sopenharmony_ci#define SW_SCIF_CAN	0
2362306a36Sopenharmony_ci#if (SW_SCIF_CAN)
2462306a36Sopenharmony_ci/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */
2562306a36Sopenharmony_ci#define SW_RSPI_CAN	0
2662306a36Sopenharmony_ci#else
2762306a36Sopenharmony_ci/* Please set SW_RSPI_CAN. Default value is 1 */
2862306a36Sopenharmony_ci#define SW_RSPI_CAN	1
2962306a36Sopenharmony_ci#endif
3062306a36Sopenharmony_ci
3162306a36Sopenharmony_ci#if (SW_SCIF_CAN && SW_RSPI_CAN)
3262306a36Sopenharmony_ci#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing"
3362306a36Sopenharmony_ci#endif
3462306a36Sopenharmony_ci
3562306a36Sopenharmony_ci/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
3662306a36Sopenharmony_ci#define PMOD1_SER0	1
3762306a36Sopenharmony_ci
3862306a36Sopenharmony_ci/*
3962306a36Sopenharmony_ci * To enable MTU3a PWM on PMOD0,
4062306a36Sopenharmony_ci *  - Set DIP-Switch SW1-4 to Off position.
4162306a36Sopenharmony_ci *  - Set SW_RSPI_CAN macro to 0.
4262306a36Sopenharmony_ci *  - Set PMOD_MTU3 macro to 1.
4362306a36Sopenharmony_ci */
4462306a36Sopenharmony_ci#define PMOD_MTU3	0
4562306a36Sopenharmony_ci
4662306a36Sopenharmony_ci#if (PMOD_MTU3 && SW_RSPI_CAN)
4762306a36Sopenharmony_ci#error "Cannot set as both PMOD_MTU3 and SW_RSPI_CAN are mutually exclusive"
4862306a36Sopenharmony_ci#endif
4962306a36Sopenharmony_ci
5062306a36Sopenharmony_ci#include "r9a07g044c2.dtsi"
5162306a36Sopenharmony_ci#include "rzg2lc-smarc-som.dtsi"
5262306a36Sopenharmony_ci#include "rzg2lc-smarc.dtsi"
5362306a36Sopenharmony_ci
5462306a36Sopenharmony_ci/ {
5562306a36Sopenharmony_ci	model = "Renesas SMARC EVK based on r9a07g044c2";
5662306a36Sopenharmony_ci	compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
5762306a36Sopenharmony_ci};
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