162306a36Sopenharmony_ci// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * IPQ9574 RDP449 board device tree source 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 662306a36Sopenharmony_ci * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 762306a36Sopenharmony_ci */ 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci/dts-v1/; 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci#include "ipq9574.dtsi" 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci/ { 1462306a36Sopenharmony_ci model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C6"; 1562306a36Sopenharmony_ci compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574"; 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ci aliases { 1862306a36Sopenharmony_ci serial0 = &blsp1_uart2; 1962306a36Sopenharmony_ci }; 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci chosen { 2262306a36Sopenharmony_ci stdout-path = "serial0:115200n8"; 2362306a36Sopenharmony_ci }; 2462306a36Sopenharmony_ci}; 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ci&blsp1_spi0 { 2762306a36Sopenharmony_ci pinctrl-0 = <&spi_0_pins>; 2862306a36Sopenharmony_ci pinctrl-names = "default"; 2962306a36Sopenharmony_ci status = "okay"; 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_ci flash@0 { 3262306a36Sopenharmony_ci compatible = "micron,n25q128a11", "jedec,spi-nor"; 3362306a36Sopenharmony_ci reg = <0>; 3462306a36Sopenharmony_ci #address-cells = <1>; 3562306a36Sopenharmony_ci #size-cells = <1>; 3662306a36Sopenharmony_ci spi-max-frequency = <50000000>; 3762306a36Sopenharmony_ci }; 3862306a36Sopenharmony_ci}; 3962306a36Sopenharmony_ci 4062306a36Sopenharmony_ci&blsp1_uart2 { 4162306a36Sopenharmony_ci pinctrl-0 = <&uart2_pins>; 4262306a36Sopenharmony_ci pinctrl-names = "default"; 4362306a36Sopenharmony_ci status = "okay"; 4462306a36Sopenharmony_ci}; 4562306a36Sopenharmony_ci 4662306a36Sopenharmony_ci&rpm_requests { 4762306a36Sopenharmony_ci regulators { 4862306a36Sopenharmony_ci compatible = "qcom,rpm-mp5496-regulators"; 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ci ipq9574_s1: s1 { 5162306a36Sopenharmony_ci /* 5262306a36Sopenharmony_ci * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. 5362306a36Sopenharmony_ci * During regulator registration, kernel not knowing the initial voltage, 5462306a36Sopenharmony_ci * considers it as zero and brings up the regulators with minimum supported voltage. 5562306a36Sopenharmony_ci * Update the regulator-min-microvolt with SVS voltage of 725mV so that 5662306a36Sopenharmony_ci * the regulators are brought up with 725mV which is sufficient for all the 5762306a36Sopenharmony_ci * corner parts to operate at 800MHz 5862306a36Sopenharmony_ci */ 5962306a36Sopenharmony_ci regulator-min-microvolt = <725000>; 6062306a36Sopenharmony_ci regulator-max-microvolt = <1075000>; 6162306a36Sopenharmony_ci }; 6262306a36Sopenharmony_ci }; 6362306a36Sopenharmony_ci}; 6462306a36Sopenharmony_ci 6562306a36Sopenharmony_ci&sleep_clk { 6662306a36Sopenharmony_ci clock-frequency = <32000>; 6762306a36Sopenharmony_ci}; 6862306a36Sopenharmony_ci 6962306a36Sopenharmony_ci&tlmm { 7062306a36Sopenharmony_ci spi_0_pins: spi-0-state { 7162306a36Sopenharmony_ci pins = "gpio11", "gpio12", "gpio13", "gpio14"; 7262306a36Sopenharmony_ci function = "blsp0_spi"; 7362306a36Sopenharmony_ci drive-strength = <8>; 7462306a36Sopenharmony_ci bias-disable; 7562306a36Sopenharmony_ci }; 7662306a36Sopenharmony_ci}; 7762306a36Sopenharmony_ci 7862306a36Sopenharmony_ci&xo_board_clk { 7962306a36Sopenharmony_ci clock-frequency = <24000000>; 8062306a36Sopenharmony_ci}; 81