162306a36Sopenharmony_ci/*
262306a36Sopenharmony_ci * ARM Ltd.
362306a36Sopenharmony_ci *
462306a36Sopenharmony_ci * ARMv8 Foundation model DTS (GICv2 configuration)
562306a36Sopenharmony_ci */
662306a36Sopenharmony_ci
762306a36Sopenharmony_ci/ {
862306a36Sopenharmony_ci	gic: interrupt-controller@2c001000 {
962306a36Sopenharmony_ci		compatible = "arm,gic-400", "arm,cortex-a15-gic";
1062306a36Sopenharmony_ci		#interrupt-cells = <3>;
1162306a36Sopenharmony_ci		#address-cells = <1>;
1262306a36Sopenharmony_ci		interrupt-controller;
1362306a36Sopenharmony_ci		reg = <0x0 0x2c001000 0 0x1000>,
1462306a36Sopenharmony_ci		      <0x0 0x2c002000 0 0x2000>,
1562306a36Sopenharmony_ci		      <0x0 0x2c004000 0 0x2000>,
1662306a36Sopenharmony_ci		      <0x0 0x2c006000 0 0x2000>;
1762306a36Sopenharmony_ci		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1862306a36Sopenharmony_ci	};
1962306a36Sopenharmony_ci};
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