162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0+ 262306a36Sopenharmony_ci * 362306a36Sopenharmony_ci * Shared SCU setup for mach-shmobile 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 2012 Bastian Hecht 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci#include <linux/linkage.h> 962306a36Sopenharmony_ci#include <linux/init.h> 1062306a36Sopenharmony_ci#include <asm/page.h> 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci/* 1362306a36Sopenharmony_ci * Boot code for secondary CPUs. 1462306a36Sopenharmony_ci * 1562306a36Sopenharmony_ci * First we turn on L1 cache coherency for our CPU. Then we jump to 1662306a36Sopenharmony_ci * secondary_startup that invalidates the cache and hands over control 1762306a36Sopenharmony_ci * to the common ARM startup code. 1862306a36Sopenharmony_ci */ 1962306a36Sopenharmony_ciENTRY(shmobile_boot_scu) 2062306a36Sopenharmony_ci @ r0 = SCU base address 2162306a36Sopenharmony_ci mrc p15, 0, r1, c0, c0, 5 @ read MPIDR 2262306a36Sopenharmony_ci and r1, r1, #3 @ mask out cpu ID 2362306a36Sopenharmony_ci lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits 2462306a36Sopenharmony_ci ldr r2, [r0, #8] @ SCU Power Status Register 2562306a36Sopenharmony_ci mov r3, #3 2662306a36Sopenharmony_ci lsl r3, r3, r1 2762306a36Sopenharmony_ci bic r2, r2, r3 @ Clear bits of our CPU (Run Mode) 2862306a36Sopenharmony_ci str r2, [r0, #8] @ write back 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ci b secondary_startup 3162306a36Sopenharmony_ciENDPROC(shmobile_boot_scu) 32