162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright 2008 Openmoko, Inc. 462306a36Sopenharmony_ci * Copyright 2008 Simtec Electronics 562306a36Sopenharmony_ci * http://armlinux.simtec.co.uk/ 662306a36Sopenharmony_ci * Ben Dooks <ben@simtec.co.uk> 762306a36Sopenharmony_ci * 862306a36Sopenharmony_ci * S3C - USB2.0 Highspeed/OtG device PHY registers 962306a36Sopenharmony_ci*/ 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci/* Note, this is a separate header file as some of the clock framework 1262306a36Sopenharmony_ci * needs to touch this if the clk_48m is used as the USB OHCI or other 1362306a36Sopenharmony_ci * peripheral source. 1462306a36Sopenharmony_ci*/ 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H 1762306a36Sopenharmony_ci#define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__ 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci/* S3C64XX_PA_USB_HSPHY */ 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci#define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY) 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci#define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00) 2462306a36Sopenharmony_ci#define S3C_PHYPWR_NORMAL_MASK (0x19 << 0) 2562306a36Sopenharmony_ci#define S3C_PHYPWR_OTG_DISABLE (1 << 4) 2662306a36Sopenharmony_ci#define S3C_PHYPWR_ANALOG_POWERDOWN (1 << 3) 2762306a36Sopenharmony_ci#define SRC_PHYPWR_FORCE_SUSPEND (1 << 1) 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci#define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04) 3062306a36Sopenharmony_ci#define S3C_PHYCLK_MODE_USB11 (1 << 6) 3162306a36Sopenharmony_ci#define S3C_PHYCLK_EXT_OSC (1 << 5) 3262306a36Sopenharmony_ci#define S3C_PHYCLK_CLK_FORCE (1 << 4) 3362306a36Sopenharmony_ci#define S3C_PHYCLK_ID_PULL (1 << 2) 3462306a36Sopenharmony_ci#define S3C_PHYCLK_CLKSEL_MASK (0x3 << 0) 3562306a36Sopenharmony_ci#define S3C_PHYCLK_CLKSEL_SHIFT (0) 3662306a36Sopenharmony_ci#define S3C_PHYCLK_CLKSEL_48M (0x0 << 0) 3762306a36Sopenharmony_ci#define S3C_PHYCLK_CLKSEL_12M (0x2 << 0) 3862306a36Sopenharmony_ci#define S3C_PHYCLK_CLKSEL_24M (0x3 << 0) 3962306a36Sopenharmony_ci 4062306a36Sopenharmony_ci#define S3C_RSTCON S3C_HSOTG_PHYREG(0x08) 4162306a36Sopenharmony_ci#define S3C_RSTCON_PHYCLK (1 << 2) 4262306a36Sopenharmony_ci#define S3C_RSTCON_HCLK (1 << 1) 4362306a36Sopenharmony_ci#define S3C_RSTCON_PHY (1 << 0) 4462306a36Sopenharmony_ci 4562306a36Sopenharmony_ci#define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20) 4662306a36Sopenharmony_ci 4762306a36Sopenharmony_ci#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */ 48