162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 462306a36Sopenharmony_ci * Author: Tony Xie <tony.xie@rock-chips.com> 562306a36Sopenharmony_ci */ 662306a36Sopenharmony_ci 762306a36Sopenharmony_ci#include <linux/linkage.h> 862306a36Sopenharmony_ci#include <asm/assembler.h> 962306a36Sopenharmony_ci#include <asm/page.h> 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci.data 1262306a36Sopenharmony_ci/* 1362306a36Sopenharmony_ci * this code will be copied from 1462306a36Sopenharmony_ci * ddr to sram for system resumeing. 1562306a36Sopenharmony_ci * so it is ".data section". 1662306a36Sopenharmony_ci */ 1762306a36Sopenharmony_ci .align 2 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ciENTRY(rockchip_slp_cpu_resume) 2062306a36Sopenharmony_ci setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off 2162306a36Sopenharmony_ci mrc p15, 0, r1, c0, c0, 5 2262306a36Sopenharmony_ci and r1, r1, #0xf 2362306a36Sopenharmony_ci cmp r1, #0 2462306a36Sopenharmony_ci /* olny cpu0 can continue to run, the others is halt here */ 2562306a36Sopenharmony_ci beq cpu0run 2662306a36Sopenharmony_cisecondary_loop: 2762306a36Sopenharmony_ci wfe 2862306a36Sopenharmony_ci b secondary_loop 2962306a36Sopenharmony_cicpu0run: 3062306a36Sopenharmony_ci ldr r3, rkpm_bootdata_l2ctlr_f 3162306a36Sopenharmony_ci cmp r3, #0 3262306a36Sopenharmony_ci beq sp_set 3362306a36Sopenharmony_ci ldr r3, rkpm_bootdata_l2ctlr 3462306a36Sopenharmony_ci mcr p15, 1, r3, c9, c0, 2 3562306a36Sopenharmony_cisp_set: 3662306a36Sopenharmony_ci ldr sp, rkpm_bootdata_cpusp 3762306a36Sopenharmony_ci ldr r1, rkpm_bootdata_cpu_code 3862306a36Sopenharmony_ci bx r1 3962306a36Sopenharmony_ciENDPROC(rockchip_slp_cpu_resume) 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ci/* Parameters filled in by the kernel */ 4262306a36Sopenharmony_ci 4362306a36Sopenharmony_ci/* Flag for whether to restore L2CTLR on resume */ 4462306a36Sopenharmony_ci .global rkpm_bootdata_l2ctlr_f 4562306a36Sopenharmony_cirkpm_bootdata_l2ctlr_f: 4662306a36Sopenharmony_ci .long 0 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_ci/* Saved L2CTLR to restore on resume */ 4962306a36Sopenharmony_ci .global rkpm_bootdata_l2ctlr 5062306a36Sopenharmony_cirkpm_bootdata_l2ctlr: 5162306a36Sopenharmony_ci .long 0 5262306a36Sopenharmony_ci 5362306a36Sopenharmony_ci/* CPU resume SP addr */ 5462306a36Sopenharmony_ci .globl rkpm_bootdata_cpusp 5562306a36Sopenharmony_cirkpm_bootdata_cpusp: 5662306a36Sopenharmony_ci .long 0 5762306a36Sopenharmony_ci 5862306a36Sopenharmony_ci/* CPU resume function (physical address) */ 5962306a36Sopenharmony_ci .globl rkpm_bootdata_cpu_code 6062306a36Sopenharmony_cirkpm_bootdata_cpu_code: 6162306a36Sopenharmony_ci .long 0 6262306a36Sopenharmony_ci 6362306a36Sopenharmony_ciENTRY(rk3288_bootram_sz) 6462306a36Sopenharmony_ci .word . - rockchip_slp_cpu_resume 65