162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Interface for functions that need to be run in internal SRAM 462306a36Sopenharmony_ci */ 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci#ifndef __ASSEMBLY__ 762306a36Sopenharmony_ci 862306a36Sopenharmony_ciextern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 962306a36Sopenharmony_ci u32 base_cs, u32 force_unlock); 1062306a36Sopenharmony_ciextern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, 1162306a36Sopenharmony_ci u32 mem_type); 1262306a36Sopenharmony_ciextern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ciextern void omap3_sram_restore_context(void); 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ciextern int __init omap_sram_init(void); 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ciextern void *omap_sram_push(void *funcp, unsigned long size); 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ciextern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 2162306a36Sopenharmony_ci u32 base_cs, u32 force_unlock); 2262306a36Sopenharmony_ciextern unsigned long omap242x_sram_ddr_init_sz; 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ciextern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, 2562306a36Sopenharmony_ci int bypass); 2662306a36Sopenharmony_ciextern unsigned long omap242x_sram_set_prcm_sz; 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ciextern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, 2962306a36Sopenharmony_ci u32 mem_type); 3062306a36Sopenharmony_ciextern unsigned long omap242x_sram_reprogram_sdrc_sz; 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ciextern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 3462306a36Sopenharmony_ci u32 base_cs, u32 force_unlock); 3562306a36Sopenharmony_ciextern unsigned long omap243x_sram_ddr_init_sz; 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ciextern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, 3862306a36Sopenharmony_ci int bypass); 3962306a36Sopenharmony_ciextern unsigned long omap243x_sram_set_prcm_sz; 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ciextern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, 4262306a36Sopenharmony_ci u32 mem_type); 4362306a36Sopenharmony_ciextern unsigned long omap243x_sram_reprogram_sdrc_sz; 4462306a36Sopenharmony_ci 4562306a36Sopenharmony_ci#ifdef CONFIG_PM 4662306a36Sopenharmony_ciextern void omap_push_sram_idle(void); 4762306a36Sopenharmony_ci#else 4862306a36Sopenharmony_cistatic inline void omap_push_sram_idle(void) {} 4962306a36Sopenharmony_ci#endif /* CONFIG_PM */ 5062306a36Sopenharmony_ci 5162306a36Sopenharmony_ci#endif /* __ASSEMBLY__ */ 5262306a36Sopenharmony_ci 5362306a36Sopenharmony_ci/* 5462306a36Sopenharmony_ci * OMAP2+: define the SRAM PA addresses. 5562306a36Sopenharmony_ci * Used by the SRAM management code and the idle sleep code. 5662306a36Sopenharmony_ci */ 5762306a36Sopenharmony_ci#define OMAP2_SRAM_PA 0x40200000 5862306a36Sopenharmony_ci#define OMAP3_SRAM_PA 0x40200000 59