162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * omap4-sar-layout.h: OMAP4 SAR RAM layout header file 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 2011 Texas Instruments, Inc. 662306a36Sopenharmony_ci * Santosh Shilimkar <santosh.shilimkar@ti.com> 762306a36Sopenharmony_ci */ 862306a36Sopenharmony_ci#ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H 962306a36Sopenharmony_ci#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci/* 1262306a36Sopenharmony_ci * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE 1362306a36Sopenharmony_ci */ 1462306a36Sopenharmony_ci#define SAR_BANK1_OFFSET 0x0000 1562306a36Sopenharmony_ci#define SAR_BANK2_OFFSET 0x1000 1662306a36Sopenharmony_ci#define SAR_BANK3_OFFSET 0x2000 1762306a36Sopenharmony_ci#define SAR_BANK4_OFFSET 0x3000 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci/* Scratch pad memory offsets from SAR_BANK1 */ 2062306a36Sopenharmony_ci#define SCU_OFFSET0 0xfe4 2162306a36Sopenharmony_ci#define SCU_OFFSET1 0xfe8 2262306a36Sopenharmony_ci#define OMAP_TYPE_OFFSET 0xfec 2362306a36Sopenharmony_ci#define L2X0_SAVE_OFFSET0 0xff0 2462306a36Sopenharmony_ci#define L2X0_SAVE_OFFSET1 0xff4 2562306a36Sopenharmony_ci#define L2X0_AUXCTRL_OFFSET 0xff8 2662306a36Sopenharmony_ci#define L2X0_PREFETCH_CTRL_OFFSET 0xffc 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ci/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK1 */ 2962306a36Sopenharmony_ci#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04 3062306a36Sopenharmony_ci#define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08 3162306a36Sopenharmony_ci#define OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xe00 3262306a36Sopenharmony_ci#define OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xe04 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ci#define SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x500) 3562306a36Sopenharmony_ci#define SAR_SECURE_RAM_SIZE_OFFSET (SAR_BANK3_OFFSET + 0x504) 3662306a36Sopenharmony_ci#define SAR_SECRAM_SAVED_AT_OFFSET (SAR_BANK3_OFFSET + 0x508) 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ci/* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */ 3962306a36Sopenharmony_ci#define WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x684) 4062306a36Sopenharmony_ci#define WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x694) 4162306a36Sopenharmony_ci#define WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6a4) 4262306a36Sopenharmony_ci#define WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6b4) 4362306a36Sopenharmony_ci#define AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x6c4) 4462306a36Sopenharmony_ci#define AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x6c8) 4562306a36Sopenharmony_ci#define PTMSYNCREQ_MASK_OFFSET (SAR_BANK3_OFFSET + 0x6cc) 4662306a36Sopenharmony_ci#define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0) 4762306a36Sopenharmony_ci#define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 4862306a36Sopenharmony_ci 4962306a36Sopenharmony_ci/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */ 5062306a36Sopenharmony_ci#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9dc) 5162306a36Sopenharmony_ci#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9f0) 5262306a36Sopenharmony_ci#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa04) 5362306a36Sopenharmony_ci#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa18) 5462306a36Sopenharmony_ci#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0xa2c) 5562306a36Sopenharmony_ci#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x930) 5662306a36Sopenharmony_ci#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0xa34) 5762306a36Sopenharmony_ci#define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800) 5862306a36Sopenharmony_ci 5962306a36Sopenharmony_ci#endif 60