162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * DRA7xx Clock Management register bits 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 662306a36Sopenharmony_ci * 762306a36Sopenharmony_ci * Generated by code originally written by: 862306a36Sopenharmony_ci * Paul Walmsley (paul@pwsan.com) 962306a36Sopenharmony_ci * Rajendra Nayak (rnayak@ti.com) 1062306a36Sopenharmony_ci * Benoit Cousson (b-cousson@ti.com) 1162306a36Sopenharmony_ci * 1262306a36Sopenharmony_ci * This file is automatically generated from the OMAP hardware databases. 1362306a36Sopenharmony_ci * We respectfully ask that any modifications to this file be coordinated 1462306a36Sopenharmony_ci * with the public linux-omap@vger.kernel.org mailing list and the 1562306a36Sopenharmony_ci * authors above to ensure that the autogeneration scripts are kept 1662306a36Sopenharmony_ci * up-to-date with the file contents. 1762306a36Sopenharmony_ci */ 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H 2062306a36Sopenharmony_ci#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci#define DRA7XX_ATL_STATDEP_SHIFT 30 2362306a36Sopenharmony_ci#define DRA7XX_CAM_STATDEP_SHIFT 9 2462306a36Sopenharmony_ci#define DRA7XX_DSP1_STATDEP_SHIFT 1 2562306a36Sopenharmony_ci#define DRA7XX_DSP2_STATDEP_SHIFT 18 2662306a36Sopenharmony_ci#define DRA7XX_DSS_STATDEP_SHIFT 8 2762306a36Sopenharmony_ci#define DRA7XX_EMIF_STATDEP_SHIFT 4 2862306a36Sopenharmony_ci#define DRA7XX_EVE1_STATDEP_SHIFT 19 2962306a36Sopenharmony_ci#define DRA7XX_EVE2_STATDEP_SHIFT 20 3062306a36Sopenharmony_ci#define DRA7XX_EVE3_STATDEP_SHIFT 21 3162306a36Sopenharmony_ci#define DRA7XX_EVE4_STATDEP_SHIFT 22 3262306a36Sopenharmony_ci#define DRA7XX_GMAC_STATDEP_SHIFT 25 3362306a36Sopenharmony_ci#define DRA7XX_GPU_STATDEP_SHIFT 10 3462306a36Sopenharmony_ci#define DRA7XX_IPU1_STATDEP_SHIFT 23 3562306a36Sopenharmony_ci#define DRA7XX_IPU2_STATDEP_SHIFT 0 3662306a36Sopenharmony_ci#define DRA7XX_IPU_STATDEP_SHIFT 24 3762306a36Sopenharmony_ci#define DRA7XX_IVA_STATDEP_SHIFT 2 3862306a36Sopenharmony_ci#define DRA7XX_L3INIT_STATDEP_SHIFT 7 3962306a36Sopenharmony_ci#define DRA7XX_L3MAIN1_STATDEP_SHIFT 5 4062306a36Sopenharmony_ci#define DRA7XX_L4CFG_STATDEP_SHIFT 12 4162306a36Sopenharmony_ci#define DRA7XX_L4PER2_STATDEP_SHIFT 26 4262306a36Sopenharmony_ci#define DRA7XX_L4PER3_STATDEP_SHIFT 27 4362306a36Sopenharmony_ci#define DRA7XX_L4PER_STATDEP_SHIFT 13 4462306a36Sopenharmony_ci#define DRA7XX_L4SEC_STATDEP_SHIFT 14 4562306a36Sopenharmony_ci#define DRA7XX_PCIE_STATDEP_SHIFT 29 4662306a36Sopenharmony_ci#define DRA7XX_VPE_STATDEP_SHIFT 28 4762306a36Sopenharmony_ci#define DRA7XX_WKUPAON_STATDEP_SHIFT 15 4862306a36Sopenharmony_ci#endif 49