162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (C) Greg Lonnon 2001 462306a36Sopenharmony_ci * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> 562306a36Sopenharmony_ci * 662306a36Sopenharmony_ci * Copyright (C) 2009 Texas Instruments 762306a36Sopenharmony_ci * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 862306a36Sopenharmony_ci * 962306a36Sopenharmony_ci * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610 1062306a36Sopenharmony_ci * are different. 1162306a36Sopenharmony_ci */ 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci#ifndef __ASM_ARCH_OMAP15XX_IRQS_H 1462306a36Sopenharmony_ci#define __ASM_ARCH_OMAP15XX_IRQS_H 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci/* 1762306a36Sopenharmony_ci * IRQ numbers for interrupt handler 1 1862306a36Sopenharmony_ci * 1962306a36Sopenharmony_ci * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below 2062306a36Sopenharmony_ci * 2162306a36Sopenharmony_ci */ 2262306a36Sopenharmony_ci#define INT_CAMERA (NR_IRQS_LEGACY + 1) 2362306a36Sopenharmony_ci#define INT_FIQ (NR_IRQS_LEGACY + 3) 2462306a36Sopenharmony_ci#define INT_RTDX (NR_IRQS_LEGACY + 6) 2562306a36Sopenharmony_ci#define INT_DSP_MMU_ABORT (NR_IRQS_LEGACY + 7) 2662306a36Sopenharmony_ci#define INT_HOST (NR_IRQS_LEGACY + 8) 2762306a36Sopenharmony_ci#define INT_ABORT (NR_IRQS_LEGACY + 9) 2862306a36Sopenharmony_ci#define INT_BRIDGE_PRIV (NR_IRQS_LEGACY + 13) 2962306a36Sopenharmony_ci#define INT_GPIO_BANK1 (NR_IRQS_LEGACY + 14) 3062306a36Sopenharmony_ci#define INT_UART3 (NR_IRQS_LEGACY + 15) 3162306a36Sopenharmony_ci#define INT_TIMER3 (NR_IRQS_LEGACY + 16) 3262306a36Sopenharmony_ci#define INT_DMA_CH0_6 (NR_IRQS_LEGACY + 19) 3362306a36Sopenharmony_ci#define INT_DMA_CH1_7 (NR_IRQS_LEGACY + 20) 3462306a36Sopenharmony_ci#define INT_DMA_CH2_8 (NR_IRQS_LEGACY + 21) 3562306a36Sopenharmony_ci#define INT_DMA_CH3 (NR_IRQS_LEGACY + 22) 3662306a36Sopenharmony_ci#define INT_DMA_CH4 (NR_IRQS_LEGACY + 23) 3762306a36Sopenharmony_ci#define INT_DMA_CH5 (NR_IRQS_LEGACY + 24) 3862306a36Sopenharmony_ci#define INT_TIMER1 (NR_IRQS_LEGACY + 26) 3962306a36Sopenharmony_ci#define INT_WD_TIMER (NR_IRQS_LEGACY + 27) 4062306a36Sopenharmony_ci#define INT_BRIDGE_PUB (NR_IRQS_LEGACY + 28) 4162306a36Sopenharmony_ci#define INT_TIMER2 (NR_IRQS_LEGACY + 30) 4262306a36Sopenharmony_ci#define INT_LCD_CTRL (NR_IRQS_LEGACY + 31) 4362306a36Sopenharmony_ci 4462306a36Sopenharmony_ci/* 4562306a36Sopenharmony_ci * OMAP-1510 specific IRQ numbers for interrupt handler 1 4662306a36Sopenharmony_ci */ 4762306a36Sopenharmony_ci#define INT_1510_IH2_IRQ (NR_IRQS_LEGACY + 0) 4862306a36Sopenharmony_ci#define INT_1510_RES2 (NR_IRQS_LEGACY + 2) 4962306a36Sopenharmony_ci#define INT_1510_SPI_TX (NR_IRQS_LEGACY + 4) 5062306a36Sopenharmony_ci#define INT_1510_SPI_RX (NR_IRQS_LEGACY + 5) 5162306a36Sopenharmony_ci#define INT_1510_DSP_MAILBOX1 (NR_IRQS_LEGACY + 10) 5262306a36Sopenharmony_ci#define INT_1510_DSP_MAILBOX2 (NR_IRQS_LEGACY + 11) 5362306a36Sopenharmony_ci#define INT_1510_RES12 (NR_IRQS_LEGACY + 12) 5462306a36Sopenharmony_ci#define INT_1510_LB_MMU (NR_IRQS_LEGACY + 17) 5562306a36Sopenharmony_ci#define INT_1510_RES18 (NR_IRQS_LEGACY + 18) 5662306a36Sopenharmony_ci#define INT_1510_LOCAL_BUS (NR_IRQS_LEGACY + 29) 5762306a36Sopenharmony_ci 5862306a36Sopenharmony_ci/* 5962306a36Sopenharmony_ci * OMAP-1610 specific IRQ numbers for interrupt handler 1 6062306a36Sopenharmony_ci */ 6162306a36Sopenharmony_ci#define INT_1610_IH2_IRQ INT_1510_IH2_IRQ 6262306a36Sopenharmony_ci#define INT_1610_IH2_FIQ (NR_IRQS_LEGACY + 2) 6362306a36Sopenharmony_ci#define INT_1610_McBSP2_TX (NR_IRQS_LEGACY + 4) 6462306a36Sopenharmony_ci#define INT_1610_McBSP2_RX (NR_IRQS_LEGACY + 5) 6562306a36Sopenharmony_ci#define INT_1610_DSP_MAILBOX1 (NR_IRQS_LEGACY + 10) 6662306a36Sopenharmony_ci#define INT_1610_DSP_MAILBOX2 (NR_IRQS_LEGACY + 11) 6762306a36Sopenharmony_ci#define INT_1610_LCD_LINE (NR_IRQS_LEGACY + 12) 6862306a36Sopenharmony_ci#define INT_1610_GPTIMER1 (NR_IRQS_LEGACY + 17) 6962306a36Sopenharmony_ci#define INT_1610_GPTIMER2 (NR_IRQS_LEGACY + 18) 7062306a36Sopenharmony_ci#define INT_1610_SSR_FIFO_0 (NR_IRQS_LEGACY + 29) 7162306a36Sopenharmony_ci 7262306a36Sopenharmony_ci/* 7362306a36Sopenharmony_ci * OMAP-7xx specific IRQ numbers for interrupt handler 1 7462306a36Sopenharmony_ci */ 7562306a36Sopenharmony_ci#define INT_7XX_IH2_FIQ (NR_IRQS_LEGACY + 0) 7662306a36Sopenharmony_ci#define INT_7XX_IH2_IRQ (NR_IRQS_LEGACY + 1) 7762306a36Sopenharmony_ci#define INT_7XX_USB_NON_ISO (NR_IRQS_LEGACY + 2) 7862306a36Sopenharmony_ci#define INT_7XX_USB_ISO (NR_IRQS_LEGACY + 3) 7962306a36Sopenharmony_ci#define INT_7XX_ICR (NR_IRQS_LEGACY + 4) 8062306a36Sopenharmony_ci#define INT_7XX_EAC (NR_IRQS_LEGACY + 5) 8162306a36Sopenharmony_ci#define INT_7XX_GPIO_BANK1 (NR_IRQS_LEGACY + 6) 8262306a36Sopenharmony_ci#define INT_7XX_GPIO_BANK2 (NR_IRQS_LEGACY + 7) 8362306a36Sopenharmony_ci#define INT_7XX_GPIO_BANK3 (NR_IRQS_LEGACY + 8) 8462306a36Sopenharmony_ci#define INT_7XX_McBSP2TX (NR_IRQS_LEGACY + 10) 8562306a36Sopenharmony_ci#define INT_7XX_McBSP2RX (NR_IRQS_LEGACY + 11) 8662306a36Sopenharmony_ci#define INT_7XX_McBSP2RX_OVF (NR_IRQS_LEGACY + 12) 8762306a36Sopenharmony_ci#define INT_7XX_LCD_LINE (NR_IRQS_LEGACY + 14) 8862306a36Sopenharmony_ci#define INT_7XX_GSM_PROTECT (NR_IRQS_LEGACY + 15) 8962306a36Sopenharmony_ci#define INT_7XX_TIMER3 (NR_IRQS_LEGACY + 16) 9062306a36Sopenharmony_ci#define INT_7XX_GPIO_BANK5 (NR_IRQS_LEGACY + 17) 9162306a36Sopenharmony_ci#define INT_7XX_GPIO_BANK6 (NR_IRQS_LEGACY + 18) 9262306a36Sopenharmony_ci#define INT_7XX_SPGIO_WR (NR_IRQS_LEGACY + 29) 9362306a36Sopenharmony_ci 9462306a36Sopenharmony_ci/* 9562306a36Sopenharmony_ci * IRQ numbers for interrupt handler 2 9662306a36Sopenharmony_ci * 9762306a36Sopenharmony_ci * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below 9862306a36Sopenharmony_ci */ 9962306a36Sopenharmony_ci#define IH2_BASE (NR_IRQS_LEGACY + 32) 10062306a36Sopenharmony_ci 10162306a36Sopenharmony_ci#define INT_KEYBOARD (1 + IH2_BASE) 10262306a36Sopenharmony_ci#define INT_uWireTX (2 + IH2_BASE) 10362306a36Sopenharmony_ci#define INT_uWireRX (3 + IH2_BASE) 10462306a36Sopenharmony_ci#define INT_I2C (4 + IH2_BASE) 10562306a36Sopenharmony_ci#define INT_MPUIO (5 + IH2_BASE) 10662306a36Sopenharmony_ci#define INT_USB_HHC_1 (6 + IH2_BASE) 10762306a36Sopenharmony_ci#define INT_McBSP3TX (10 + IH2_BASE) 10862306a36Sopenharmony_ci#define INT_McBSP3RX (11 + IH2_BASE) 10962306a36Sopenharmony_ci#define INT_McBSP1TX (12 + IH2_BASE) 11062306a36Sopenharmony_ci#define INT_McBSP1RX (13 + IH2_BASE) 11162306a36Sopenharmony_ci#define INT_UART1 (14 + IH2_BASE) 11262306a36Sopenharmony_ci#define INT_UART2 (15 + IH2_BASE) 11362306a36Sopenharmony_ci#define INT_BT_MCSI1TX (16 + IH2_BASE) 11462306a36Sopenharmony_ci#define INT_BT_MCSI1RX (17 + IH2_BASE) 11562306a36Sopenharmony_ci#define INT_SOSSI_MATCH (19 + IH2_BASE) 11662306a36Sopenharmony_ci#define INT_USB_W2FC (20 + IH2_BASE) 11762306a36Sopenharmony_ci#define INT_1WIRE (21 + IH2_BASE) 11862306a36Sopenharmony_ci#define INT_OS_TIMER (22 + IH2_BASE) 11962306a36Sopenharmony_ci#define INT_MMC (23 + IH2_BASE) 12062306a36Sopenharmony_ci#define INT_GAUGE_32K (24 + IH2_BASE) 12162306a36Sopenharmony_ci#define INT_RTC_TIMER (25 + IH2_BASE) 12262306a36Sopenharmony_ci#define INT_RTC_ALARM (26 + IH2_BASE) 12362306a36Sopenharmony_ci#define INT_MEM_STICK (27 + IH2_BASE) 12462306a36Sopenharmony_ci 12562306a36Sopenharmony_ci/* 12662306a36Sopenharmony_ci * OMAP-1510 specific IRQ numbers for interrupt handler 2 12762306a36Sopenharmony_ci */ 12862306a36Sopenharmony_ci#define INT_1510_DSP_MMU (28 + IH2_BASE) 12962306a36Sopenharmony_ci#define INT_1510_COM_SPI_RO (31 + IH2_BASE) 13062306a36Sopenharmony_ci 13162306a36Sopenharmony_ci/* 13262306a36Sopenharmony_ci * OMAP-1610 specific IRQ numbers for interrupt handler 2 13362306a36Sopenharmony_ci */ 13462306a36Sopenharmony_ci#define INT_1610_FAC (0 + IH2_BASE) 13562306a36Sopenharmony_ci#define INT_1610_USB_HHC_2 (7 + IH2_BASE) 13662306a36Sopenharmony_ci#define INT_1610_USB_OTG (8 + IH2_BASE) 13762306a36Sopenharmony_ci#define INT_1610_SoSSI (9 + IH2_BASE) 13862306a36Sopenharmony_ci#define INT_1610_SoSSI_MATCH (19 + IH2_BASE) 13962306a36Sopenharmony_ci#define INT_1610_DSP_MMU (28 + IH2_BASE) 14062306a36Sopenharmony_ci#define INT_1610_McBSP2RX_OF (31 + IH2_BASE) 14162306a36Sopenharmony_ci#define INT_1610_STI (32 + IH2_BASE) 14262306a36Sopenharmony_ci#define INT_1610_STI_WAKEUP (33 + IH2_BASE) 14362306a36Sopenharmony_ci#define INT_1610_GPTIMER3 (34 + IH2_BASE) 14462306a36Sopenharmony_ci#define INT_1610_GPTIMER4 (35 + IH2_BASE) 14562306a36Sopenharmony_ci#define INT_1610_GPTIMER5 (36 + IH2_BASE) 14662306a36Sopenharmony_ci#define INT_1610_GPTIMER6 (37 + IH2_BASE) 14762306a36Sopenharmony_ci#define INT_1610_GPTIMER7 (38 + IH2_BASE) 14862306a36Sopenharmony_ci#define INT_1610_GPTIMER8 (39 + IH2_BASE) 14962306a36Sopenharmony_ci#define INT_1610_GPIO_BANK2 (40 + IH2_BASE) 15062306a36Sopenharmony_ci#define INT_1610_GPIO_BANK3 (41 + IH2_BASE) 15162306a36Sopenharmony_ci#define INT_1610_MMC2 (42 + IH2_BASE) 15262306a36Sopenharmony_ci#define INT_1610_CF (43 + IH2_BASE) 15362306a36Sopenharmony_ci#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE) 15462306a36Sopenharmony_ci#define INT_1610_GPIO_BANK4 (48 + IH2_BASE) 15562306a36Sopenharmony_ci#define INT_1610_SPI (49 + IH2_BASE) 15662306a36Sopenharmony_ci#define INT_1610_DMA_CH6 (53 + IH2_BASE) 15762306a36Sopenharmony_ci#define INT_1610_DMA_CH7 (54 + IH2_BASE) 15862306a36Sopenharmony_ci#define INT_1610_DMA_CH8 (55 + IH2_BASE) 15962306a36Sopenharmony_ci#define INT_1610_DMA_CH9 (56 + IH2_BASE) 16062306a36Sopenharmony_ci#define INT_1610_DMA_CH10 (57 + IH2_BASE) 16162306a36Sopenharmony_ci#define INT_1610_DMA_CH11 (58 + IH2_BASE) 16262306a36Sopenharmony_ci#define INT_1610_DMA_CH12 (59 + IH2_BASE) 16362306a36Sopenharmony_ci#define INT_1610_DMA_CH13 (60 + IH2_BASE) 16462306a36Sopenharmony_ci#define INT_1610_DMA_CH14 (61 + IH2_BASE) 16562306a36Sopenharmony_ci#define INT_1610_DMA_CH15 (62 + IH2_BASE) 16662306a36Sopenharmony_ci#define INT_1610_NAND (63 + IH2_BASE) 16762306a36Sopenharmony_ci#define INT_1610_SHA1MD5 (91 + IH2_BASE) 16862306a36Sopenharmony_ci 16962306a36Sopenharmony_ci/* 17062306a36Sopenharmony_ci * OMAP-7xx specific IRQ numbers for interrupt handler 2 17162306a36Sopenharmony_ci */ 17262306a36Sopenharmony_ci#define INT_7XX_HW_ERRORS (0 + IH2_BASE) 17362306a36Sopenharmony_ci#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE) 17462306a36Sopenharmony_ci#define INT_7XX_CFCD (2 + IH2_BASE) 17562306a36Sopenharmony_ci#define INT_7XX_CFIREQ (3 + IH2_BASE) 17662306a36Sopenharmony_ci#define INT_7XX_I2C (4 + IH2_BASE) 17762306a36Sopenharmony_ci#define INT_7XX_PCC (5 + IH2_BASE) 17862306a36Sopenharmony_ci#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE) 17962306a36Sopenharmony_ci#define INT_7XX_SPI_100K_1 (7 + IH2_BASE) 18062306a36Sopenharmony_ci#define INT_7XX_SYREN_SPI (8 + IH2_BASE) 18162306a36Sopenharmony_ci#define INT_7XX_VLYNQ (9 + IH2_BASE) 18262306a36Sopenharmony_ci#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE) 18362306a36Sopenharmony_ci#define INT_7XX_McBSP1TX (11 + IH2_BASE) 18462306a36Sopenharmony_ci#define INT_7XX_McBSP1RX (12 + IH2_BASE) 18562306a36Sopenharmony_ci#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE) 18662306a36Sopenharmony_ci#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE) 18762306a36Sopenharmony_ci#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE) 18862306a36Sopenharmony_ci#define INT_7XX_MCSI (16 + IH2_BASE) 18962306a36Sopenharmony_ci#define INT_7XX_uWireTX (17 + IH2_BASE) 19062306a36Sopenharmony_ci#define INT_7XX_uWireRX (18 + IH2_BASE) 19162306a36Sopenharmony_ci#define INT_7XX_SMC_CD (19 + IH2_BASE) 19262306a36Sopenharmony_ci#define INT_7XX_SMC_IREQ (20 + IH2_BASE) 19362306a36Sopenharmony_ci#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE) 19462306a36Sopenharmony_ci#define INT_7XX_TIMER32K (22 + IH2_BASE) 19562306a36Sopenharmony_ci#define INT_7XX_MMC_SDIO (23 + IH2_BASE) 19662306a36Sopenharmony_ci#define INT_7XX_UPLD (24 + IH2_BASE) 19762306a36Sopenharmony_ci#define INT_7XX_USB_HHC_1 (27 + IH2_BASE) 19862306a36Sopenharmony_ci#define INT_7XX_USB_HHC_2 (28 + IH2_BASE) 19962306a36Sopenharmony_ci#define INT_7XX_USB_GENI (29 + IH2_BASE) 20062306a36Sopenharmony_ci#define INT_7XX_USB_OTG (30 + IH2_BASE) 20162306a36Sopenharmony_ci#define INT_7XX_CAMERA_IF (31 + IH2_BASE) 20262306a36Sopenharmony_ci#define INT_7XX_RNG (32 + IH2_BASE) 20362306a36Sopenharmony_ci#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE) 20462306a36Sopenharmony_ci#define INT_7XX_DBB_RF_EN (34 + IH2_BASE) 20562306a36Sopenharmony_ci#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE) 20662306a36Sopenharmony_ci#define INT_7XX_SHA1_MD5 (36 + IH2_BASE) 20762306a36Sopenharmony_ci#define INT_7XX_SPI_100K_2 (37 + IH2_BASE) 20862306a36Sopenharmony_ci#define INT_7XX_RNG_IDLE (38 + IH2_BASE) 20962306a36Sopenharmony_ci#define INT_7XX_MPUIO (39 + IH2_BASE) 21062306a36Sopenharmony_ci#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) 21162306a36Sopenharmony_ci#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE) 21262306a36Sopenharmony_ci#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE) 21362306a36Sopenharmony_ci#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE) 21462306a36Sopenharmony_ci#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE) 21562306a36Sopenharmony_ci#define INT_7XX_DMA_CH6 (53 + IH2_BASE) 21662306a36Sopenharmony_ci#define INT_7XX_DMA_CH7 (54 + IH2_BASE) 21762306a36Sopenharmony_ci#define INT_7XX_DMA_CH8 (55 + IH2_BASE) 21862306a36Sopenharmony_ci#define INT_7XX_DMA_CH9 (56 + IH2_BASE) 21962306a36Sopenharmony_ci#define INT_7XX_DMA_CH10 (57 + IH2_BASE) 22062306a36Sopenharmony_ci#define INT_7XX_DMA_CH11 (58 + IH2_BASE) 22162306a36Sopenharmony_ci#define INT_7XX_DMA_CH12 (59 + IH2_BASE) 22262306a36Sopenharmony_ci#define INT_7XX_DMA_CH13 (60 + IH2_BASE) 22362306a36Sopenharmony_ci#define INT_7XX_DMA_CH14 (61 + IH2_BASE) 22462306a36Sopenharmony_ci#define INT_7XX_DMA_CH15 (62 + IH2_BASE) 22562306a36Sopenharmony_ci#define INT_7XX_NAND (63 + IH2_BASE) 22662306a36Sopenharmony_ci 22762306a36Sopenharmony_ci/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and 22862306a36Sopenharmony_ci * 16 MPUIO lines */ 22962306a36Sopenharmony_ci#define OMAP_MAX_GPIO_LINES 192 23062306a36Sopenharmony_ci#define IH_GPIO_BASE (128 + IH2_BASE) 23162306a36Sopenharmony_ci#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) 23262306a36Sopenharmony_ci#define OMAP_IRQ_END (IH_MPUIO_BASE + 16) 23362306a36Sopenharmony_ci 23462306a36Sopenharmony_ci#define OMAP_IRQ_BIT(irq) (1 << ((irq - NR_IRQS_LEGACY) % 32)) 23562306a36Sopenharmony_ci 23662306a36Sopenharmony_ci#ifdef CONFIG_FIQ 23762306a36Sopenharmony_ci#define FIQ_START 1024 23862306a36Sopenharmony_ci#endif 23962306a36Sopenharmony_ci 24062306a36Sopenharmony_ci#endif 241