162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (C) 2014 Marvell 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 662306a36Sopenharmony_ci * Gregory Clement <gregory.clement@free-electrons.com> 762306a36Sopenharmony_ci */ 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci#include <linux/linkage.h> 1062306a36Sopenharmony_ci#include <asm/assembler.h> 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ciENTRY(armada_38x_scu_power_up) 1462306a36Sopenharmony_ci mrc p15, 4, r1, c15, c0 @ get SCU base address 1562306a36Sopenharmony_ci orr r1, r1, #0x8 @ SCU CPU Power Status Register 1662306a36Sopenharmony_ci mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID 1762306a36Sopenharmony_ci and r0, r0, #15 1862306a36Sopenharmony_ci add r1, r1, r0 1962306a36Sopenharmony_ci mov r0, #0x0 2062306a36Sopenharmony_ci strb r0, [r1] @ switch SCU power state to Normal mode 2162306a36Sopenharmony_ci ret lr 2262306a36Sopenharmony_ciENDPROC(armada_38x_scu_power_up) 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ci/* 2562306a36Sopenharmony_ci * This is the entry point through which CPUs exiting cpuidle deep 2662306a36Sopenharmony_ci * idle state are going. 2762306a36Sopenharmony_ci */ 2862306a36Sopenharmony_ciENTRY(armada_370_xp_cpu_resume) 2962306a36Sopenharmony_ciARM_BE8(setend be ) @ go BE8 if entered LE 3062306a36Sopenharmony_ci /* 3162306a36Sopenharmony_ci * Disable the MMU that might have been enabled in BootROM if 3262306a36Sopenharmony_ci * this code is used in the resume path of a suspend/resume 3362306a36Sopenharmony_ci * cycle. 3462306a36Sopenharmony_ci */ 3562306a36Sopenharmony_ci mrc p15, 0, r1, c1, c0, 0 3662306a36Sopenharmony_ci bic r1, #1 3762306a36Sopenharmony_ci mcr p15, 0, r1, c1, c0, 0 3862306a36Sopenharmony_ci bl ll_add_cpu_to_smp_group 3962306a36Sopenharmony_ci bl ll_enable_coherency 4062306a36Sopenharmony_ci b cpu_resume 4162306a36Sopenharmony_ciENDPROC(armada_370_xp_cpu_resume) 4262306a36Sopenharmony_ci 4362306a36Sopenharmony_ciENTRY(armada_38x_cpu_resume) 4462306a36Sopenharmony_ci /* do we need it for Armada 38x*/ 4562306a36Sopenharmony_ciARM_BE8(setend be ) @ go BE8 if entered LE 4662306a36Sopenharmony_ci bl v7_invalidate_l1 4762306a36Sopenharmony_ci bl armada_38x_scu_power_up 4862306a36Sopenharmony_ci b cpu_resume 4962306a36Sopenharmony_ciENDPROC(armada_38x_cpu_resume) 5062306a36Sopenharmony_ci 5162306a36Sopenharmony_ci.global mvebu_boot_wa_start 5262306a36Sopenharmony_ci.global mvebu_boot_wa_end 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ci/* The following code will be executed from SRAM */ 5562306a36Sopenharmony_ciENTRY(mvebu_boot_wa_start) 5662306a36Sopenharmony_ciARM_BE8(setend be) 5762306a36Sopenharmony_ci adr r0, 1f 5862306a36Sopenharmony_ci ldr r0, [r0] @ load the address of the 5962306a36Sopenharmony_ci @ resume register 6062306a36Sopenharmony_ci ldr r0, [r0] @ load the value in the 6162306a36Sopenharmony_ci @ resume register 6262306a36Sopenharmony_ciARM_BE8(rev r0, r0) @ the value is stored LE 6362306a36Sopenharmony_ci mov pc, r0 @ jump to this value 6462306a36Sopenharmony_ci/* 6562306a36Sopenharmony_ci * the last word of this piece of code will be filled by the physical 6662306a36Sopenharmony_ci * address of the boot address register just after being copied in SRAM 6762306a36Sopenharmony_ci */ 6862306a36Sopenharmony_ci1: 6962306a36Sopenharmony_ci .long . 7062306a36Sopenharmony_cimvebu_boot_wa_end: 7162306a36Sopenharmony_ciENDPROC(mvebu_boot_wa_end) 72