162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * SMP support: Entry point for secondary CPUs 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 2012 Marvell 662306a36Sopenharmony_ci * 762306a36Sopenharmony_ci * Yehuda Yitschak <yehuday@marvell.com> 862306a36Sopenharmony_ci * Gregory CLEMENT <gregory.clement@free-electrons.com> 962306a36Sopenharmony_ci * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 1062306a36Sopenharmony_ci * 1162306a36Sopenharmony_ci * This file implements the assembly entry point for secondary CPUs in 1262306a36Sopenharmony_ci * an SMP kernel. The only thing we need to do is to add the CPU to 1362306a36Sopenharmony_ci * the coherency fabric by writing to 2 registers. Currently the base 1462306a36Sopenharmony_ci * register addresses are hard coded due to the early initialisation 1562306a36Sopenharmony_ci * problems. 1662306a36Sopenharmony_ci */ 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci#include <linux/linkage.h> 1962306a36Sopenharmony_ci#include <linux/init.h> 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci#include <asm/assembler.h> 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci/* 2462306a36Sopenharmony_ci * Armada XP specific entry point for secondary CPUs. 2562306a36Sopenharmony_ci * We add the CPU to the coherency fabric and then jump to secondary 2662306a36Sopenharmony_ci * startup 2762306a36Sopenharmony_ci */ 2862306a36Sopenharmony_ciENTRY(armada_xp_secondary_startup) 2962306a36Sopenharmony_ci ARM_BE8(setend be ) @ go BE8 if entered LE 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_ci bl ll_add_cpu_to_smp_group 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ci bl ll_enable_coherency 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci b secondary_startup 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ciENDPROC(armada_xp_secondary_startup) 38