162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (c) 2012 Samsung Electronics. 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Exynos - SMC Call 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci#ifndef __ASM_ARCH_EXYNOS_SMC_H 962306a36Sopenharmony_ci#define __ASM_ARCH_EXYNOS_SMC_H 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci#define SMC_CMD_INIT (-1) 1262306a36Sopenharmony_ci#define SMC_CMD_INFO (-2) 1362306a36Sopenharmony_ci/* For Power Management */ 1462306a36Sopenharmony_ci#define SMC_CMD_SLEEP (-3) 1562306a36Sopenharmony_ci#define SMC_CMD_CPU1BOOT (-4) 1662306a36Sopenharmony_ci#define SMC_CMD_CPU0AFTR (-5) 1762306a36Sopenharmony_ci#define SMC_CMD_SAVE (-6) 1862306a36Sopenharmony_ci#define SMC_CMD_SHUTDOWN (-7) 1962306a36Sopenharmony_ci/* For CP15 Access */ 2062306a36Sopenharmony_ci#define SMC_CMD_C15RESUME (-11) 2162306a36Sopenharmony_ci/* For L2 Cache Access */ 2262306a36Sopenharmony_ci#define SMC_CMD_L2X0CTRL (-21) 2362306a36Sopenharmony_ci#define SMC_CMD_L2X0SETUP1 (-22) 2462306a36Sopenharmony_ci#define SMC_CMD_L2X0SETUP2 (-23) 2562306a36Sopenharmony_ci#define SMC_CMD_L2X0INVALL (-24) 2662306a36Sopenharmony_ci#define SMC_CMD_L2X0DEBUG (-25) 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ci/* For Accessing CP15/SFR (General) */ 2962306a36Sopenharmony_ci#define SMC_CMD_REG (-101) 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_ci/* defines for SMC_CMD_REG */ 3262306a36Sopenharmony_ci#define SMC_REG_CLASS_SFR_W (0x1 << 30) 3362306a36Sopenharmony_ci#define SMC_REG_ID_SFR_W(addr) (SMC_REG_CLASS_SFR_W | ((addr) >> 2)) 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci#ifndef __ASSEMBLY__ 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ciextern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3); 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_ci#endif /* __ASSEMBLY__ */ 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ci/* op type for SMC_CMD_SAVE and SMC_CMD_SHUTDOWN */ 4262306a36Sopenharmony_ci#define OP_TYPE_CORE 0x0 4362306a36Sopenharmony_ci#define OP_TYPE_CLUSTER 0x1 4462306a36Sopenharmony_ci 4562306a36Sopenharmony_ci/* Power State required for SMC_CMD_SAVE and SMC_CMD_SHUTDOWN */ 4662306a36Sopenharmony_ci#define SMC_POWERSTATE_IDLE 0x1 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_ci#endif 49