162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci *  Cloned from linux/arch/arm/mach-realview/headsmp.S
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci *  Copyright (c) 2003 ARM Limited
662306a36Sopenharmony_ci *  All Rights Reserved
762306a36Sopenharmony_ci */
862306a36Sopenharmony_ci#include <linux/linkage.h>
962306a36Sopenharmony_ci#include <linux/init.h>
1062306a36Sopenharmony_ci
1162306a36Sopenharmony_ci#include <asm/assembler.h>
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ci/*
1462306a36Sopenharmony_ci * exynos4 specific entry point for secondary CPUs.  This provides
1562306a36Sopenharmony_ci * a "holding pen" into which all secondary cores are held until we're
1662306a36Sopenharmony_ci * ready for them to initialise.
1762306a36Sopenharmony_ci */
1862306a36Sopenharmony_ciENTRY(exynos4_secondary_startup)
1962306a36Sopenharmony_ciARM_BE8(setend	be)
2062306a36Sopenharmony_ci	mrc	p15, 0, r0, c0, c0, 5
2162306a36Sopenharmony_ci	and	r0, r0, #15
2262306a36Sopenharmony_ci	adr	r4, 1f
2362306a36Sopenharmony_ci	ldmia	r4, {r5, r6}
2462306a36Sopenharmony_ci	sub	r4, r4, r5
2562306a36Sopenharmony_ci	add	r6, r6, r4
2662306a36Sopenharmony_cipen:	ldr	r7, [r6]
2762306a36Sopenharmony_ci	cmp	r7, r0
2862306a36Sopenharmony_ci	bne	pen
2962306a36Sopenharmony_ci
3062306a36Sopenharmony_ci	/*
3162306a36Sopenharmony_ci	 * we've been released from the holding pen: secondary_stack
3262306a36Sopenharmony_ci	 * should now contain the SVC stack for this core
3362306a36Sopenharmony_ci	 */
3462306a36Sopenharmony_ci	b	secondary_startup
3562306a36Sopenharmony_ciENDPROC(exynos4_secondary_startup)
3662306a36Sopenharmony_ci
3762306a36Sopenharmony_ci	.align 2
3862306a36Sopenharmony_ci1:	.long	.
3962306a36Sopenharmony_ci	.long	exynos_pen_release
40