162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * arch/arm/mach-ep93xx/include/mach/hardware.h 462306a36Sopenharmony_ci */ 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci#ifndef __ASM_ARCH_HARDWARE_H 762306a36Sopenharmony_ci#define __ASM_ARCH_HARDWARE_H 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci#include "platform.h" 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci/* 1262306a36Sopenharmony_ci * The EP93xx has two external crystal oscillators. To generate the 1362306a36Sopenharmony_ci * required high-frequency clocks, the processor uses two phase-locked- 1462306a36Sopenharmony_ci * loops (PLLs) to multiply the incoming external clock signal to much 1562306a36Sopenharmony_ci * higher frequencies that are then divided down by programmable dividers 1662306a36Sopenharmony_ci * to produce the needed clocks. The PLLs operate independently of one 1762306a36Sopenharmony_ci * another. 1862306a36Sopenharmony_ci */ 1962306a36Sopenharmony_ci#define EP93XX_EXT_CLK_RATE 14745600 2062306a36Sopenharmony_ci#define EP93XX_EXT_RTC_RATE 32768 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci#define EP93XX_KEYTCHCLK_DIV4 (EP93XX_EXT_CLK_RATE / 4) 2362306a36Sopenharmony_ci#define EP93XX_KEYTCHCLK_DIV16 (EP93XX_EXT_CLK_RATE / 16) 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci#endif 26