162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * TI DaVinci clock definitions 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 2006-2007 Texas Instruments. 662306a36Sopenharmony_ci * Copyright (C) 2008-2009 Deep Root Systems, LLC 762306a36Sopenharmony_ci */ 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci#ifndef __ARCH_ARM_DAVINCI_CLOCK_H 1062306a36Sopenharmony_ci#define __ARCH_ARM_DAVINCI_CLOCK_H 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci/* PLL/Reset register offsets */ 1362306a36Sopenharmony_ci#define PLLCTL 0x100 1462306a36Sopenharmony_ci#define PLLCTL_PLLEN BIT(0) 1562306a36Sopenharmony_ci#define PLLCTL_PLLPWRDN BIT(1) 1662306a36Sopenharmony_ci#define PLLCTL_PLLRST BIT(3) 1762306a36Sopenharmony_ci#define PLLCTL_PLLDIS BIT(4) 1862306a36Sopenharmony_ci#define PLLCTL_PLLENSRC BIT(5) 1962306a36Sopenharmony_ci#define PLLCTL_CLKMODE BIT(8) 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci#define PLLM 0x110 2262306a36Sopenharmony_ci#define PLLM_PLLM_MASK 0xff 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ci#define PREDIV 0x114 2562306a36Sopenharmony_ci#define PLLDIV1 0x118 2662306a36Sopenharmony_ci#define PLLDIV2 0x11c 2762306a36Sopenharmony_ci#define PLLDIV3 0x120 2862306a36Sopenharmony_ci#define POSTDIV 0x128 2962306a36Sopenharmony_ci#define BPDIV 0x12c 3062306a36Sopenharmony_ci#define PLLCMD 0x138 3162306a36Sopenharmony_ci#define PLLSTAT 0x13c 3262306a36Sopenharmony_ci#define PLLALNCTL 0x140 3362306a36Sopenharmony_ci#define PLLDCHANGE 0x144 3462306a36Sopenharmony_ci#define PLLCKEN 0x148 3562306a36Sopenharmony_ci#define PLLCKSTAT 0x14c 3662306a36Sopenharmony_ci#define PLLSYSTAT 0x150 3762306a36Sopenharmony_ci#define PLLDIV4 0x160 3862306a36Sopenharmony_ci#define PLLDIV5 0x164 3962306a36Sopenharmony_ci#define PLLDIV6 0x168 4062306a36Sopenharmony_ci#define PLLDIV7 0x16c 4162306a36Sopenharmony_ci#define PLLDIV8 0x170 4262306a36Sopenharmony_ci#define PLLDIV9 0x174 4362306a36Sopenharmony_ci#define PLLDIV_EN BIT(15) 4462306a36Sopenharmony_ci#define PLLDIV_RATIO_MASK 0x1f 4562306a36Sopenharmony_ci 4662306a36Sopenharmony_ci/* 4762306a36Sopenharmony_ci * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN 4862306a36Sopenharmony_ci * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us 4962306a36Sopenharmony_ci * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input 5062306a36Sopenharmony_ci * is ~25MHz. Units are micro seconds. 5162306a36Sopenharmony_ci */ 5262306a36Sopenharmony_ci#define PLL_BYPASS_TIME 1 5362306a36Sopenharmony_ci/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */ 5462306a36Sopenharmony_ci#define PLL_RESET_TIME 1 5562306a36Sopenharmony_ci/* 5662306a36Sopenharmony_ci * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4 5762306a36Sopenharmony_ci * Units are micro seconds. 5862306a36Sopenharmony_ci */ 5962306a36Sopenharmony_ci#define PLL_LOCK_TIME 20 6062306a36Sopenharmony_ci 6162306a36Sopenharmony_ci#endif 62