162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-or-later 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Broadcom BCM63138 PMB initialization for secondary CPU(s) 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 2015 Broadcom Corporation 662306a36Sopenharmony_ci * Author: Florian Fainelli <f.fainelli@gmail.com> 762306a36Sopenharmony_ci */ 862306a36Sopenharmony_ci#include <linux/kernel.h> 962306a36Sopenharmony_ci#include <linux/io.h> 1062306a36Sopenharmony_ci#include <linux/spinlock.h> 1162306a36Sopenharmony_ci#include <linux/reset/bcm63xx_pmb.h> 1262306a36Sopenharmony_ci#include <linux/of.h> 1362306a36Sopenharmony_ci#include <linux/of_address.h> 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ci#include "bcm63xx_smp.h" 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ci/* ARM Control register definitions */ 1862306a36Sopenharmony_ci#define CORE_PWR_CTRL_SHIFT 0 1962306a36Sopenharmony_ci#define CORE_PWR_CTRL_MASK 0x3 2062306a36Sopenharmony_ci#define PLL_PWR_ON BIT(8) 2162306a36Sopenharmony_ci#define PLL_LDO_PWR_ON BIT(9) 2262306a36Sopenharmony_ci#define PLL_CLAMP_ON BIT(10) 2362306a36Sopenharmony_ci#define CPU_RESET_N(x) BIT(13 + (x)) 2462306a36Sopenharmony_ci#define NEON_RESET_N BIT(15) 2562306a36Sopenharmony_ci#define PWR_CTRL_STATUS_SHIFT 28 2662306a36Sopenharmony_ci#define PWR_CTRL_STATUS_MASK 0x3 2762306a36Sopenharmony_ci#define PWR_DOWN_SHIFT 30 2862306a36Sopenharmony_ci#define PWR_DOWN_MASK 0x3 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ci/* CPU Power control register definitions */ 3162306a36Sopenharmony_ci#define MEM_PWR_OK BIT(0) 3262306a36Sopenharmony_ci#define MEM_PWR_ON BIT(1) 3362306a36Sopenharmony_ci#define MEM_CLAMP_ON BIT(2) 3462306a36Sopenharmony_ci#define MEM_PWR_OK_STATUS BIT(4) 3562306a36Sopenharmony_ci#define MEM_PWR_ON_STATUS BIT(5) 3662306a36Sopenharmony_ci#define MEM_PDA_SHIFT 8 3762306a36Sopenharmony_ci#define MEM_PDA_MASK 0xf 3862306a36Sopenharmony_ci#define MEM_PDA_CPU_MASK 0x1 3962306a36Sopenharmony_ci#define MEM_PDA_NEON_MASK 0xf 4062306a36Sopenharmony_ci#define CLAMP_ON BIT(15) 4162306a36Sopenharmony_ci#define PWR_OK_SHIFT 16 4262306a36Sopenharmony_ci#define PWR_OK_MASK 0xf 4362306a36Sopenharmony_ci#define PWR_ON_SHIFT 20 4462306a36Sopenharmony_ci#define PWR_CPU_MASK 0x03 4562306a36Sopenharmony_ci#define PWR_NEON_MASK 0x01 4662306a36Sopenharmony_ci#define PWR_ON_MASK 0xf 4762306a36Sopenharmony_ci#define PWR_OK_STATUS_SHIFT 24 4862306a36Sopenharmony_ci#define PWR_OK_STATUS_MASK 0xf 4962306a36Sopenharmony_ci#define PWR_ON_STATUS_SHIFT 28 5062306a36Sopenharmony_ci#define PWR_ON_STATUS_MASK 0xf 5162306a36Sopenharmony_ci 5262306a36Sopenharmony_ci#define ARM_CONTROL 0x30 5362306a36Sopenharmony_ci#define ARM_PWR_CONTROL_BASE 0x34 5462306a36Sopenharmony_ci#define ARM_PWR_CONTROL(x) (ARM_PWR_CONTROL_BASE + (x) * 0x4) 5562306a36Sopenharmony_ci#define ARM_NEON_L2 0x3c 5662306a36Sopenharmony_ci 5762306a36Sopenharmony_ci/* Perform a value write, then spin until the value shifted by 5862306a36Sopenharmony_ci * shift is seen, masked with mask and is different from cond. 5962306a36Sopenharmony_ci */ 6062306a36Sopenharmony_cistatic int bpcm_wr_rd_mask(void __iomem *master, 6162306a36Sopenharmony_ci unsigned int addr, u32 off, u32 *val, 6262306a36Sopenharmony_ci u32 shift, u32 mask, u32 cond) 6362306a36Sopenharmony_ci{ 6462306a36Sopenharmony_ci int ret; 6562306a36Sopenharmony_ci 6662306a36Sopenharmony_ci ret = bpcm_wr(master, addr, off, *val); 6762306a36Sopenharmony_ci if (ret) 6862306a36Sopenharmony_ci return ret; 6962306a36Sopenharmony_ci 7062306a36Sopenharmony_ci do { 7162306a36Sopenharmony_ci ret = bpcm_rd(master, addr, off, val); 7262306a36Sopenharmony_ci if (ret) 7362306a36Sopenharmony_ci return ret; 7462306a36Sopenharmony_ci 7562306a36Sopenharmony_ci cpu_relax(); 7662306a36Sopenharmony_ci } while (((*val >> shift) & mask) != cond); 7762306a36Sopenharmony_ci 7862306a36Sopenharmony_ci return ret; 7962306a36Sopenharmony_ci} 8062306a36Sopenharmony_ci 8162306a36Sopenharmony_ci/* Global lock to serialize accesses to the PMB registers while we 8262306a36Sopenharmony_ci * are bringing up the secondary CPU 8362306a36Sopenharmony_ci */ 8462306a36Sopenharmony_cistatic DEFINE_SPINLOCK(pmb_lock); 8562306a36Sopenharmony_ci 8662306a36Sopenharmony_cistatic int bcm63xx_pmb_get_resources(struct device_node *dn, 8762306a36Sopenharmony_ci void __iomem **base, 8862306a36Sopenharmony_ci unsigned int *cpu, 8962306a36Sopenharmony_ci unsigned int *addr) 9062306a36Sopenharmony_ci{ 9162306a36Sopenharmony_ci struct of_phandle_args args; 9262306a36Sopenharmony_ci int ret; 9362306a36Sopenharmony_ci 9462306a36Sopenharmony_ci *cpu = of_get_cpu_hwid(dn, 0); 9562306a36Sopenharmony_ci if (*cpu == ~0U) { 9662306a36Sopenharmony_ci pr_err("CPU is missing a reg node\n"); 9762306a36Sopenharmony_ci return -ENODEV; 9862306a36Sopenharmony_ci } 9962306a36Sopenharmony_ci 10062306a36Sopenharmony_ci ret = of_parse_phandle_with_args(dn, "resets", "#reset-cells", 10162306a36Sopenharmony_ci 0, &args); 10262306a36Sopenharmony_ci if (ret) { 10362306a36Sopenharmony_ci pr_err("CPU is missing a resets phandle\n"); 10462306a36Sopenharmony_ci return ret; 10562306a36Sopenharmony_ci } 10662306a36Sopenharmony_ci 10762306a36Sopenharmony_ci if (args.args_count != 2) { 10862306a36Sopenharmony_ci pr_err("reset-controller does not conform to reset-cells\n"); 10962306a36Sopenharmony_ci return -EINVAL; 11062306a36Sopenharmony_ci } 11162306a36Sopenharmony_ci 11262306a36Sopenharmony_ci *base = of_iomap(args.np, 0); 11362306a36Sopenharmony_ci if (!*base) { 11462306a36Sopenharmony_ci pr_err("failed remapping PMB register\n"); 11562306a36Sopenharmony_ci return -ENOMEM; 11662306a36Sopenharmony_ci } 11762306a36Sopenharmony_ci 11862306a36Sopenharmony_ci /* We do not need the number of zones */ 11962306a36Sopenharmony_ci *addr = args.args[0]; 12062306a36Sopenharmony_ci 12162306a36Sopenharmony_ci return 0; 12262306a36Sopenharmony_ci} 12362306a36Sopenharmony_ci 12462306a36Sopenharmony_ciint bcm63xx_pmb_power_on_cpu(struct device_node *dn) 12562306a36Sopenharmony_ci{ 12662306a36Sopenharmony_ci void __iomem *base; 12762306a36Sopenharmony_ci unsigned int cpu, addr; 12862306a36Sopenharmony_ci unsigned long flags; 12962306a36Sopenharmony_ci u32 val, ctrl; 13062306a36Sopenharmony_ci int ret; 13162306a36Sopenharmony_ci 13262306a36Sopenharmony_ci ret = bcm63xx_pmb_get_resources(dn, &base, &cpu, &addr); 13362306a36Sopenharmony_ci if (ret) 13462306a36Sopenharmony_ci return ret; 13562306a36Sopenharmony_ci 13662306a36Sopenharmony_ci /* We would not know how to enable a third and greater CPU */ 13762306a36Sopenharmony_ci WARN_ON(cpu > 1); 13862306a36Sopenharmony_ci 13962306a36Sopenharmony_ci spin_lock_irqsave(&pmb_lock, flags); 14062306a36Sopenharmony_ci 14162306a36Sopenharmony_ci /* Check if the CPU is already on and save the ARM_CONTROL register 14262306a36Sopenharmony_ci * value since we will use it later for CPU de-assert once done with 14362306a36Sopenharmony_ci * the CPU-specific power sequence 14462306a36Sopenharmony_ci */ 14562306a36Sopenharmony_ci ret = bpcm_rd(base, addr, ARM_CONTROL, &ctrl); 14662306a36Sopenharmony_ci if (ret) 14762306a36Sopenharmony_ci goto out; 14862306a36Sopenharmony_ci 14962306a36Sopenharmony_ci if (ctrl & CPU_RESET_N(cpu)) { 15062306a36Sopenharmony_ci pr_info("PMB: CPU%d is already powered on\n", cpu); 15162306a36Sopenharmony_ci ret = 0; 15262306a36Sopenharmony_ci goto out; 15362306a36Sopenharmony_ci } 15462306a36Sopenharmony_ci 15562306a36Sopenharmony_ci /* Power on PLL */ 15662306a36Sopenharmony_ci ret = bpcm_rd(base, addr, ARM_PWR_CONTROL(cpu), &val); 15762306a36Sopenharmony_ci if (ret) 15862306a36Sopenharmony_ci goto out; 15962306a36Sopenharmony_ci 16062306a36Sopenharmony_ci val |= (PWR_CPU_MASK << PWR_ON_SHIFT); 16162306a36Sopenharmony_ci 16262306a36Sopenharmony_ci ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val, 16362306a36Sopenharmony_ci PWR_ON_STATUS_SHIFT, PWR_CPU_MASK, PWR_CPU_MASK); 16462306a36Sopenharmony_ci if (ret) 16562306a36Sopenharmony_ci goto out; 16662306a36Sopenharmony_ci 16762306a36Sopenharmony_ci val |= (PWR_CPU_MASK << PWR_OK_SHIFT); 16862306a36Sopenharmony_ci 16962306a36Sopenharmony_ci ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val, 17062306a36Sopenharmony_ci PWR_OK_STATUS_SHIFT, PWR_CPU_MASK, PWR_CPU_MASK); 17162306a36Sopenharmony_ci if (ret) 17262306a36Sopenharmony_ci goto out; 17362306a36Sopenharmony_ci 17462306a36Sopenharmony_ci val &= ~CLAMP_ON; 17562306a36Sopenharmony_ci 17662306a36Sopenharmony_ci ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val); 17762306a36Sopenharmony_ci if (ret) 17862306a36Sopenharmony_ci goto out; 17962306a36Sopenharmony_ci 18062306a36Sopenharmony_ci /* Power on CPU<N> RAM */ 18162306a36Sopenharmony_ci val &= ~(MEM_PDA_MASK << MEM_PDA_SHIFT); 18262306a36Sopenharmony_ci 18362306a36Sopenharmony_ci ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val); 18462306a36Sopenharmony_ci if (ret) 18562306a36Sopenharmony_ci goto out; 18662306a36Sopenharmony_ci 18762306a36Sopenharmony_ci val |= MEM_PWR_ON; 18862306a36Sopenharmony_ci 18962306a36Sopenharmony_ci ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val, 19062306a36Sopenharmony_ci 0, MEM_PWR_ON_STATUS, MEM_PWR_ON_STATUS); 19162306a36Sopenharmony_ci if (ret) 19262306a36Sopenharmony_ci goto out; 19362306a36Sopenharmony_ci 19462306a36Sopenharmony_ci val |= MEM_PWR_OK; 19562306a36Sopenharmony_ci 19662306a36Sopenharmony_ci ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val, 19762306a36Sopenharmony_ci 0, MEM_PWR_OK_STATUS, MEM_PWR_OK_STATUS); 19862306a36Sopenharmony_ci if (ret) 19962306a36Sopenharmony_ci goto out; 20062306a36Sopenharmony_ci 20162306a36Sopenharmony_ci val &= ~MEM_CLAMP_ON; 20262306a36Sopenharmony_ci 20362306a36Sopenharmony_ci ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val); 20462306a36Sopenharmony_ci if (ret) 20562306a36Sopenharmony_ci goto out; 20662306a36Sopenharmony_ci 20762306a36Sopenharmony_ci /* De-assert CPU reset */ 20862306a36Sopenharmony_ci ctrl |= CPU_RESET_N(cpu); 20962306a36Sopenharmony_ci 21062306a36Sopenharmony_ci ret = bpcm_wr(base, addr, ARM_CONTROL, ctrl); 21162306a36Sopenharmony_ciout: 21262306a36Sopenharmony_ci spin_unlock_irqrestore(&pmb_lock, flags); 21362306a36Sopenharmony_ci iounmap(base); 21462306a36Sopenharmony_ci return ret; 21562306a36Sopenharmony_ci} 216