xref: /kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/am335x-baltos-ir5221.dts

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
 */

/*
 * VScom OnRISC
 * http://www.vscom.de
 */

/dts-v1/;

#include "am335x-baltos.dtsi"
#include "am335x-baltos-leds.dtsi"

/ {
	model = "OnRISC Baltos iR 5221";
};

&am33xx_pinmux {
	tca6416_pins: tca6416-pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7)      /* xdma_event_intr1.gpio0[20] tca6416 stuff */
		>;
	};


	dcan1_pins: dcan1-pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2)      /* uart0_ctsn.dcan1_tx_mux0 */
			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2)      /* uart0_rtsn.dcan1_rx_mux0 */
		>;
	};

	uart1_pins: uart1-pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* lcd_vsync.gpio2[22] DTR */
			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_hsync.gpio2[23] DSR */
			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_pclk.gpio2[24] DCD */
			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_ac_bias_en.gpio2[25] RI */
		>;
	};

	uart2_pins: uart2-pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)      /* spi0_sclk.uart2_rxd_mux3 */
			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)      /* spi0_d0.uart2_txd_mux3 */
			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* i2c0_sda.uart2_ctsn_mux0 */
			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* i2c0_scl.uart2_rtsn_mux0 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad12.gpio1[12] DTR */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad13.gpio1[13] DSR */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad14.gpio1[14] DCD */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad15.gpio1[15] RI */

			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7)      /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
		>;
	};

	mmc1_pins: mmc1-pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7)     /* MMC1 CD */
		>;
	};
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
	dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
	dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
	dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
	rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;

	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
	dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
	dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
	dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
	rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;

	status = "okay";
};

&i2c1 {
	tca6416: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gpio0>;
		interrupts = <20 IRQ_TYPE_EDGE_RISING>;
		pinctrl-names = "default";
		pinctrl-0 = <&tca6416_pins>;
		gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3",
				  "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3",
				  "ModeA0", "ModeA1", "ModeA2", "ModeA3",
				  "ModeB0", "ModeB1", "ModeB2", "ModeB3";
	};
};

&usb0_phy {
	status = "okay";
};

&usb1_phy {
	status = "okay";
};

&usb0 {
	status = "okay";
	dr_mode = "host";
};

&usb1 {
	status = "okay";
	dr_mode = "host";
};

&cpsw_port1 {
	phy-mode = "rmii";
	ti,dual-emac-pvid = <1>;
	fixed-link {
		speed = <100>;
		full-duplex;
	};
};

&cpsw_port2 {
	phy-mode = "rgmii-id";
	ti,dual-emac-pvid = <2>;
	phy-handle = <&phy1>;
};

&dcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&dcan1_pins>;

	status = "okay";
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
};

&gpio0 {
	gpio-line-names =
		"MDIO",
		"MDC",
		"UART2_RX",
		"UART2_TX",
		"I2C1_SDA",
		"I2C1_SCL",
		"WLAN_BTN",
		"W_DISABLE",
		"NC",
		"NC",
		"NC",
		"NC",
		"UART1_CTSN",
		"UART1_RTSN",
		"UART1_RX",
		"UART1_TX",
		"onrisc:blue:wlan",
		"onrisc:green:app",
		"USB0_DRVVBUS",
		"ETH2_INT",
		"TCA6416_INT",
		"RMII1_TXD1",
		"MMC1_DAT0",
		"MMC1_DAT1",
		"NC",
		"NC",
		"MMC1_DAT2",
		"MMC1_DAT3",
		"RMII1_TXD0",
		"NC",
		"GPMC_WAIT0",
		"GPMC_WP_N";
};

&gpio1 {
	gpio-line-names =
		"GPMC_AD0",
		"GPMC_AD1",
		"GPMC_AD2",
		"GPMC_AD3",
		"GPMC_AD4",
		"GPMC_AD5",
		"GPMC_AD6",
		"GPMC_AD7",
		"DCAN1_TX",
		"DCAN1_RX",
		"CONSOLE_RX",
		"CONSOLE_TX",
		"UART2_DTR",
		"UART2_DSR",
		"UART2_DCD",
		"UART2_RI",
		"RGMII2_TCTL",
		"RGMII2_RCTL",
		"RGMII2_TD3",
		"RGMII2_TD2",
		"RGMII2_TD1",
		"RGMII2_TD0",
		"RGMII2_TCLK",
		"RGMII2_RCLK",
		"RGMII2_RD3",
		"RGMII2_RD2",
		"RGMII2_RD1",
		"RGMII2_RD0",
		"PMIC_INT1",
		"GPMC_CSN0_Flash",
		"MMC1_CLK",
		"MMC1_CMD";
};

&gpio2 {
	gpio-line-names =
		"GPMC_CSN3_BUS",
		"GPMC_CLK",
		"GPMC_ADVN_ALE",
		"GPMC_OEN_RE_N",
		"GPMC_WE_N",
		"GPMC_BEN0_CLE",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"SD_CD",
		"SD_WP",
		"RMII1_RXD1",
		"RMII1_RXD0",
		"UART1_DTR",
		"UART1_DSR",
		"UART1_DCD",
		"UART1_RI",
		"MMC0_DAT3",
		"MMC0_DAT2",
		"MMC0_DAT1",
		"MMC0_DAT0",
		"MMC0_CLK",
		"MMC0_CMD";
};

&gpio3 {
	gpio-line-names =
		"onrisc:red:power",
		"RMII1_CRS_DV",
		"RMII1_RXER",
		"RMII1_TXEN",
		"3G_PWR_EN",
		"UART2_CTSN",
		"UART2_RTSN",
		"WLAN_IRQ",
		"WLAN_EN",
		"NC",
		"NC",
		"NC",
		"NC",
		"USB1_DRVVBUS",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC",
		"NC";
};