162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-or-later
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Copyright (c) 2020 thingy.jp.
462306a36Sopenharmony_ci * Author: Daniel Palmer <daniel@thingy.jp>
562306a36Sopenharmony_ci */
662306a36Sopenharmony_ci
762306a36Sopenharmony_ci#include "mstar-infinity.dtsi"
862306a36Sopenharmony_ci
962306a36Sopenharmony_ci&cpu0_opp_table {
1062306a36Sopenharmony_ci		opp-1000000000 {
1162306a36Sopenharmony_ci			opp-hz = /bits/ 64 <1000000000>;
1262306a36Sopenharmony_ci			opp-microvolt = <1000000>;
1362306a36Sopenharmony_ci			clock-latency-ns = <300000>;
1462306a36Sopenharmony_ci		};
1562306a36Sopenharmony_ci
1662306a36Sopenharmony_ci		opp-1200000000 {
1762306a36Sopenharmony_ci			opp-hz = /bits/ 64 <1200000000>;
1862306a36Sopenharmony_ci			opp-microvolt = <1000000>;
1962306a36Sopenharmony_ci			clock-latency-ns = <300000>;
2062306a36Sopenharmony_ci		};
2162306a36Sopenharmony_ci};
2262306a36Sopenharmony_ci
2362306a36Sopenharmony_ci&cpus {
2462306a36Sopenharmony_ci	cpu1: cpu@1 {
2562306a36Sopenharmony_ci		device_type = "cpu";
2662306a36Sopenharmony_ci		compatible = "arm,cortex-a7";
2762306a36Sopenharmony_ci		operating-points-v2 = <&cpu0_opp_table>;
2862306a36Sopenharmony_ci		reg = <0x1>;
2962306a36Sopenharmony_ci		clocks = <&cpupll>;
3062306a36Sopenharmony_ci		clock-names = "cpuclk";
3162306a36Sopenharmony_ci	};
3262306a36Sopenharmony_ci};
3362306a36Sopenharmony_ci
3462306a36Sopenharmony_ci&riu {
3562306a36Sopenharmony_ci	smpctrl: smpctrl@204000 {
3662306a36Sopenharmony_ci		reg = <0x204000 0x200>;
3762306a36Sopenharmony_ci		status = "disabled";
3862306a36Sopenharmony_ci	};
3962306a36Sopenharmony_ci};
40