162306a36Sopenharmony_ci/* 262306a36Sopenharmony_ci * NXP LPC4350 and LPC4330 SoC 362306a36Sopenharmony_ci * 462306a36Sopenharmony_ci * Copyright 2015 Ariel D'Alessandro <ariel.dalessandro@gmail.com> 562306a36Sopenharmony_ci * 662306a36Sopenharmony_ci * This code is released using a dual license strategy: BSD/GPL 762306a36Sopenharmony_ci * You can choose the licence that better fits your requirements. 862306a36Sopenharmony_ci * 962306a36Sopenharmony_ci * Released under the terms of 3-clause BSD License 1062306a36Sopenharmony_ci * Released under the terms of GNU General Public License Version 2.0 1162306a36Sopenharmony_ci * 1262306a36Sopenharmony_ci */ 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci/ { 1562306a36Sopenharmony_ci compatible = "nxp,lpc4350", "nxp,lpc4330"; 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ci cpus { 1862306a36Sopenharmony_ci cpu@0 { 1962306a36Sopenharmony_ci compatible = "arm,cortex-m4"; 2062306a36Sopenharmony_ci }; 2162306a36Sopenharmony_ci }; 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci soc { 2462306a36Sopenharmony_ci sram0: sram@10000000 { 2562306a36Sopenharmony_ci compatible = "mmio-sram"; 2662306a36Sopenharmony_ci reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */ 2762306a36Sopenharmony_ci }; 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci sram1: sram@10080000 { 3062306a36Sopenharmony_ci compatible = "mmio-sram"; 3162306a36Sopenharmony_ci reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */ 3262306a36Sopenharmony_ci }; 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ci sram2: sram@20000000 { 3562306a36Sopenharmony_ci compatible = "mmio-sram"; 3662306a36Sopenharmony_ci reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ 3762306a36Sopenharmony_ci }; 3862306a36Sopenharmony_ci }; 3962306a36Sopenharmony_ci}; 40